11 lines
250 B
VHDL
11 lines
250 B
VHDL
-- generated by newgenasym Thu Apr 23 11:02:22 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ellie_ports is
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port (
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SMELLIE_DELAY_IN: OUT STD_LOGIC;
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TELLIE_DELAY_IN: OUT STD_LOGIC);
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end ellie_ports;
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