Tubii_Tk2/worklib/ext_trigs/entity/verilog.v

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214 B
Verilog

// generated by newgenasym Sat Mar 07 19:14:49 2015
module ext_trigs (ext_trig_in, ext_trig_out);
input [0:15] ext_trig_in;
output [0:15] ext_trig_out;
initial
begin
end
endmodule