11 lines
272 B
VHDL
11 lines
272 B
VHDL
-- generated by newgenasym Sat Mar 07 19:14:49 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ext_trigs is
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port (
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EXT_TRIG_IN: IN STD_LOGIC_VECTOR (0 TO 15);
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EXT_TRIG_OUT: OUT STD_LOGIC_VECTOR (0 TO 15));
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end ext_trigs;
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