65 lines
2.9 KiB
CSS
65 lines
2.9 KiB
CSS
C 625 400 "CHANGE_CLK_P" 645 377 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 333 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "CHANGE_CLK_P" 565 377 0.00 0.00 47 0 0 2 0 0 1 0 99
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C -625 -425 "MAX_COUNT<0..7>" -645 -448 0 1 47 0 R
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X "VHDL_MODE" "IN" -645 -492 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "MAX_COUNT<0..7>" -565 -448 0.00 0.00 47 0 0 0 0 0 1 0 99
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C -625 -350 "DATA_RDY" -645 -373 0 1 47 0 R
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X "VHDL_MODE" "IN" -645 -417 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "DATA_RDY" -565 -373 0.00 0.00 47 0 0 0 0 0 1 0 99
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C -625 50 "CLK_RESET_ECL" -645 27 0 1 47 0 R
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X "VHDL_MODE" "IN" -645 -17 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "CLK_RESET_ECL" -565 27 0.00 0.00 47 0 0 0 0 0 1 0 99
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C -625 -25 "CLK_RESET_TTL" -645 -48 0 1 47 0 R
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X "VHDL_MODE" "IN" -645 -92 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "CLK_RESET_TTL" -565 -48 0.00 0.00 47 0 0 0 0 0 1 0 99
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C -625 425 "DEFAULT_CLK" -645 402 0 1 47 0 R
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X "VHDL_MODE" "IN" -645 358 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "DEFAULT_CLK" -565 402 0.00 0.00 47 0 0 0 0 0 1 0 99
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C -625 325 "BCKP_CLK" -645 302 0 1 47 0 R
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X "VHDL_MODE" "IN" -645 258 0.00 0.00 47 0 0 2 0 0 1 0 99
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X "PIN_TEXT" "BCKP_CLK" -565 302 0.00 0.00 47 0 0 0 0 0 1 0 99
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C 625 350 "CHANGE_CLK_N" 645 327 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 283 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "CHANGE_CLK_N" 565 327 0.00 0.00 47 0 0 2 0 0 1 0 99
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C 625 225 "DEFAULT_CLK2_P" 645 202 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 158 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "DEFAULT_CLK2_P" 565 202 0.00 0.00 47 0 0 2 0 0 1 0 99
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C 625 175 "DEFAULT_CLK2_N" 645 152 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 108 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "DEFAULT_CLK2_N" 565 152 0.00 0.00 47 0 0 2 0 0 1 0 99
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C 625 0 "BCKP_CLK2_P" 645 -23 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 -67 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "BCKP_CLK2_P" 565 -23 0.00 0.00 47 0 0 2 0 0 1 0 99
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C 625 -50 "BCKP_CLK2_N" 645 -73 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 -117 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "BCKP_CLK2_N" 565 -73 0.00 0.00 47 0 0 2 0 0 1 0 99
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C 625 -175 "BCKP_CLK3_P" 645 -198 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 -242 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "BCKP_CLK3_P" 565 -198 0.00 0.00 47 0 0 2 0 0 1 0 99
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C 625 -250 "BCKP_CLK3_N" 645 -273 0 1 47 0 L
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X "VHDL_MODE" "OUT" 645 -317 0.00 0.00 47 0 0 0 0 0 1 0 99
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X "PIN_TEXT" "BCKP_CLK3_N" 565 -273 0.00 0.00 47 0 0 2 0 0 1 0 99
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L 625 -175 575 -175 -1 16
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L 575 -475 575 675 -1 16
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L 625 0 575 0 -1 16
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L 625 225 575 225 -1 16
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L -575 675 -575 -475 -1 16
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L -575 575 575 575 -1 16
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L -625 325 -575 325 -1 16
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L -625 425 -575 425 -1 16
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L -625 50 -575 50 -1 16
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L -625 -25 -575 -25 -1 16
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L -625 -350 -575 -350 -1 16
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L -625 -425 -575 -425 -1 16
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L 625 400 575 400 -1 16
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L -575 -475 575 -475 -1 16
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L 575 675 -575 675 -1 16
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A 600 -250 25 0.00 359.91 74
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A 600 -50 25 0.00 359.91 74
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A 600 175 25 0.00 359.91 74
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A 600 350 25 0.00 359.91 74
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T 0 615 0.00 0.00 47 0 0 1 0 15 0
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FAULT_DETECTION
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P "BLOCK" "TRUE" 0 10 0.00 0.00 47 0 0 1 0 0 0 0 99
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