73 lines
2.7 KiB
VHDL
73 lines
2.7 KiB
VHDL
-- generated by newgenasym Mon May 18 15:57:44 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity front_ports is
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port (
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CAEN_OUT_ANAL: IN STD_LOGIC_VECTOR (0 TO 7);
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CLK100_N: IN STD_LOGIC;
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CLK100_P: IN STD_LOGIC;
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DGT_N: IN STD_LOGIC;
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DGT_P: IN STD_LOGIC;
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ECL_TO_LVDS_IN: OUT STD_LOGIC;
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ECL_TO_LVDS_OUT_N: IN STD_LOGIC;
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ECL_TO_LVDS_OUT_P: IN STD_LOGIC;
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ECL_TO_NIM_IN: OUT STD_LOGIC;
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ECL_TO_NIM_OUT: IN STD_LOGIC;
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ECL_TO_TTL_IN: OUT STD_LOGIC;
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ECL_TO_TTL_OUT: IN STD_LOGIC;
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EXT_PED_IN: OUT STD_LOGIC;
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EXT_PED_OUT: IN STD_LOGIC;
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EXT_TRIG_IN: OUT STD_LOGIC_VECTOR (0 TO 15);
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GENERIC_DELAY_IN: OUT STD_LOGIC;
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GENERIC_DELAY_OUT: IN STD_LOGIC;
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GENERIC_PULSE_OUT: IN STD_LOGIC;
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GT_N: OUT STD_LOGIC;
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GT_NIM: IN STD_LOGIC;
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GT_P: OUT STD_LOGIC;
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GT_TTL_OUT: IN STD_LOGIC;
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LO_STAR_OUT_N: IN STD_LOGIC;
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LO_STAR_OUT_P: IN STD_LOGIC;
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LVDS_TO_ECL_IN_N: OUT STD_LOGIC;
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LVDS_TO_ECL_IN_P: OUT STD_LOGIC;
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LVDS_TO_ECL_OUT: IN STD_LOGIC;
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MTCA_MIMIC1_OUT_N: IN STD_LOGIC;
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MTCA_MIMIC1_OUT_P: IN STD_LOGIC;
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MTCA_MIMIC1_PULSE_ANAL: OUT STD_LOGIC;
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MTCA_MIMIC2_OUT_N: IN STD_LOGIC;
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MTCA_MIMIC2_OUT_P: IN STD_LOGIC;
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MTCA_MIMIC2_PULSE_ANAL: OUT STD_LOGIC;
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\mtcd_lo*\: OUT STD_LOGIC;
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NIM_TO_ECL_IN: OUT STD_LOGIC;
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NIM_TO_ECL_OUT: IN STD_LOGIC;
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PULSE_IN_ANAL: OUT STD_LOGIC_VECTOR (0 TO 11);
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PULSE_INV_IN: OUT STD_LOGIC;
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PULSE_INV_OUT: IN STD_LOGIC;
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RIBBON_PULSE_IN_N: OUT STD_LOGIC;
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RIBBON_PULSE_IN_P: OUT STD_LOGIC;
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RIBBON_PULSE_OUT_N: IN STD_LOGIC;
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RIBBON_PULSE_OUT_P: IN STD_LOGIC;
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SCALER: IN STD_LOGIC_VECTOR (1 TO 6);
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SCOPE_OUT_ANAL: IN STD_LOGIC_VECTOR (0 TO 7);
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SMELLIE_DELAY_IN: OUT STD_LOGIC;
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SMELLIE_DELAY_OUT: IN STD_LOGIC;
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SMELLIE_PULSE_OUT: IN STD_LOGIC;
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SYNC24_LVDS_N: IN STD_LOGIC;
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SYNC24_LVDS_P: IN STD_LOGIC;
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SYNC24_N: OUT STD_LOGIC;
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SYNC24_P: OUT STD_LOGIC;
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SYNC_LVDS_N: IN STD_LOGIC;
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SYNC_LVDS_P: IN STD_LOGIC;
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SYNC_N: OUT STD_LOGIC;
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SYNC_P: OUT STD_LOGIC;
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TELLIE_DELAY_IN: OUT STD_LOGIC;
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TELLIE_DELAY_OUT: IN STD_LOGIC;
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TELLIE_PULSE_OUT: IN STD_LOGIC;
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TTL_TO_ECL_IN: OUT STD_LOGIC;
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TTL_TO_ECL_OUT: IN STD_LOGIC;
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TUB_CLK_IN_N: OUT STD_LOGIC;
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TUB_CLK_IN_P: OUT STD_LOGIC;
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TUBII_RT_OUT: IN STD_LOGIC);
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end front_ports;
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