47 lines
1.3 KiB
Verilog
47 lines
1.3 KiB
Verilog
// generated by newgenasym Thu Mar 05 15:15:57 2015
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module general_utilities (clk, data, ecl_to_lvds_in, ecl_to_lvds_out_n,
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ecl_to_lvds_out_p, ecl_to_nim_in, ecl_to_nim_out,
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ecl_to_ttl_in, ecl_to_ttl_out, generic_delay_in,
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generic_delay_out, generic_pulse_in, generic_pulse_out,
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le, lvds_to_ecl_in_n, lvds_to_ecl_in_p, lvds_to_ecl_out,
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nim_to_ecl_in, nim_to_ecl_out, pulse_inv_in,
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pulse_inv_out, ribbon_pulse_in_n, ribbon_pulse_in_p,
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ribbon_pulse_out_n, ribbon_pulse_out_p, ttl_to_ecl_in,
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ttl_to_ecl_out);
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input clk;
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input data;
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input ecl_to_lvds_in;
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output ecl_to_lvds_out_n;
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output ecl_to_lvds_out_p;
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input ecl_to_nim_in;
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output ecl_to_nim_out;
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input ecl_to_ttl_in;
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output ecl_to_ttl_out;
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input generic_delay_in;
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output generic_delay_out;
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input generic_pulse_in;
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output generic_pulse_out;
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input le;
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input lvds_to_ecl_in_n;
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input lvds_to_ecl_in_p;
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output lvds_to_ecl_out;
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input nim_to_ecl_in;
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output nim_to_ecl_out;
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input pulse_inv_in;
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output pulse_inv_out;
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input ribbon_pulse_in_n;
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input ribbon_pulse_in_p;
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output ribbon_pulse_out_n;
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output ribbon_pulse_out_p;
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input ttl_to_ecl_in;
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output ttl_to_ecl_out;
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initial
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begin
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end
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endmodule
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