1200 lines
27 KiB
Plaintext
1200 lines
27 KiB
Plaintext
FILE_TYPE = MACRO_DRAWING;
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SET COLOR_WIRE YELLOW;
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SET COLOR_PROP MONO;
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SET COLOR_DOT WHITE;
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SET COLOR_ARC YELLOW;
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SET COLOR_BODY GREEN;
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SET COLOR_NOTE MONO;
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SET PROP_DISPLAY VALUE;
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SET PAGE_NUMBER P1;
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FORCEADD PULSE_INVERTER..1
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(1475 1300);
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FORCEPROP 2 LAST PATH I1
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J 0
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(1775 1775);
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DISPLAY 1.021277 (1775 1775);
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PAINT ORANGE (1775 1775);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(1475 1310);
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DISPLAY INVISIBLE (1475 1310);
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FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 0
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(1475 1300);
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DISPLAY INVISIBLE (1475 1300);
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FORCEPROP 1 LASTPIN (1025 1400) VHDL_MODE IN
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J 2
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(1005 1333);
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DISPLAY INVISIBLE (1005 1333);
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FORCEPROP 1 LASTPIN (1925 1300) VHDL_MODE OUT
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J 0
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(1945 1233);
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DISPLAY INVISIBLE (1945 1233);
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FORCEADD INPORT..1
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(-400 2550);
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FORCEPROP 1 LASTPIN (-350 2550) VHDL_PORT IN
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J 0
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(-335 2480);
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DISPLAY 0.872340 (-335 2480);
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PAINT PINK (-335 2480);
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DISPLAY INVISIBLE (-335 2480);
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FORCEPROP 1 LASTPIN (-350 2550) HDL_PORT IN
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J 0
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(-75 2425);
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DISPLAY 0.872340 (-75 2425);
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PAINT ORANGE (-75 2425);
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DISPLAY INVISIBLE (-75 2425);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(-75 2425);
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DISPLAY 0.872340 (-75 2425);
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PAINT ORANGE (-75 2425);
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DISPLAY INVISIBLE (-75 2425);
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FORCEPROP 1 LAST PATH I10
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J 0
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(-425 2600);
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DISPLAY 0.872340 (-425 2600);
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PAINT PINK (-425 2600);
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DISPLAY INVISIBLE (-425 2600);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-400 2550);
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DISPLAY INVISIBLE (-400 2550);
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FORCEADD INPORT..1
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(-400 2450);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(-75 2325);
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DISPLAY 0.872340 (-75 2325);
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PAINT ORANGE (-75 2325);
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DISPLAY INVISIBLE (-75 2325);
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FORCEPROP 1 LASTPIN (-350 2450) HDL_PORT IN
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J 0
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(-75 2325);
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DISPLAY 0.872340 (-75 2325);
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PAINT ORANGE (-75 2325);
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DISPLAY INVISIBLE (-75 2325);
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FORCEPROP 1 LASTPIN (-350 2450) VHDL_PORT IN
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J 0
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(-335 2380);
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DISPLAY 0.872340 (-335 2380);
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PAINT PINK (-335 2380);
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DISPLAY INVISIBLE (-335 2380);
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FORCEPROP 1 LAST PATH I11
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J 0
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(-425 2500);
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DISPLAY 0.872340 (-425 2500);
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PAINT PINK (-425 2500);
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DISPLAY INVISIBLE (-425 2500);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-400 2450);
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DISPLAY INVISIBLE (-400 2450);
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FORCEADD INPORT..1
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(-250 4050);
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FORCEPROP 1 LASTPIN (-200 4050) VHDL_PORT IN
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J 0
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(-185 3980);
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DISPLAY 0.872340 (-185 3980);
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PAINT PINK (-185 3980);
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DISPLAY INVISIBLE (-185 3980);
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FORCEPROP 1 LASTPIN (-200 4050) HDL_PORT IN
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J 0
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(75 3925);
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DISPLAY 0.872340 (75 3925);
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PAINT ORANGE (75 3925);
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DISPLAY INVISIBLE (75 3925);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(75 3925);
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DISPLAY 0.872340 (75 3925);
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PAINT ORANGE (75 3925);
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DISPLAY INVISIBLE (75 3925);
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FORCEPROP 1 LAST PATH I12
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J 0
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(-275 4100);
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DISPLAY 0.872340 (-275 4100);
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PAINT PINK (-275 4100);
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DISPLAY INVISIBLE (-275 4100);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-250 4050);
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DISPLAY INVISIBLE (-250 4050);
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FORCEADD INPORT..1
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(-250 3950);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(75 3825);
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DISPLAY 0.872340 (75 3825);
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PAINT ORANGE (75 3825);
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DISPLAY INVISIBLE (75 3825);
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FORCEPROP 1 LASTPIN (-200 3950) HDL_PORT IN
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J 0
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(75 3825);
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DISPLAY 0.872340 (75 3825);
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PAINT ORANGE (75 3825);
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DISPLAY INVISIBLE (75 3825);
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FORCEPROP 1 LASTPIN (-200 3950) VHDL_PORT IN
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J 0
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(-185 3880);
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DISPLAY 0.872340 (-185 3880);
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PAINT PINK (-185 3880);
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DISPLAY INVISIBLE (-185 3880);
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FORCEPROP 1 LAST PATH I13
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J 0
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(-275 4000);
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DISPLAY 0.872340 (-275 4000);
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PAINT PINK (-275 4000);
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DISPLAY INVISIBLE (-275 4000);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(-250 3950);
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DISPLAY INVISIBLE (-250 3950);
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FORCEADD OUTPORT..1
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(3250 3900);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(3575 3775);
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DISPLAY 0.872340 (3575 3775);
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PAINT ORANGE (3575 3775);
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DISPLAY INVISIBLE (3575 3775);
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FORCEPROP 1 LASTPIN (3200 3900) HDL_PORT OUT
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J 0
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(3575 3775);
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DISPLAY 0.872340 (3575 3775);
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PAINT ORANGE (3575 3775);
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DISPLAY INVISIBLE (3575 3775);
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FORCEPROP 1 LASTPIN (3200 3900) VHDL_PORT OUT
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J 0
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(3215 3830);
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DISPLAY 0.872340 (3215 3830);
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PAINT PINK (3215 3830);
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DISPLAY INVISIBLE (3215 3830);
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FORCEPROP 1 LAST PATH I14
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J 0
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(3250 3950);
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DISPLAY 0.872340 (3250 3950);
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PAINT PINK (3250 3950);
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DISPLAY INVISIBLE (3250 3950);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(3250 3900);
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DISPLAY INVISIBLE (3250 3900);
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FORCEADD OUTPORT..1
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(3275 4075);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(3600 3950);
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DISPLAY 0.872340 (3600 3950);
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PAINT ORANGE (3600 3950);
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DISPLAY INVISIBLE (3600 3950);
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FORCEPROP 1 LASTPIN (3225 4075) HDL_PORT OUT
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J 0
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(3600 3950);
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DISPLAY 0.872340 (3600 3950);
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PAINT ORANGE (3600 3950);
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DISPLAY INVISIBLE (3600 3950);
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FORCEPROP 1 LASTPIN (3225 4075) VHDL_PORT OUT
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J 0
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(3240 4005);
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DISPLAY 0.872340 (3240 4005);
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PAINT PINK (3240 4005);
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DISPLAY INVISIBLE (3240 4005);
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FORCEPROP 1 LAST PATH I15
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J 0
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(3275 4125);
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DISPLAY 0.872340 (3275 4125);
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PAINT PINK (3275 4125);
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DISPLAY INVISIBLE (3275 4125);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(3275 4075);
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DISPLAY INVISIBLE (3275 4075);
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FORCEADD OUTPORT..1
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(2950 2175);
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FORCEPROP 1 LASTPIN (2900 2175) VHDL_PORT OUT
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J 0
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(2915 2105);
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DISPLAY 0.872340 (2915 2105);
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PAINT PINK (2915 2105);
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DISPLAY INVISIBLE (2915 2105);
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FORCEPROP 1 LASTPIN (2900 2175) HDL_PORT OUT
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J 0
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(3275 2050);
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DISPLAY 0.872340 (3275 2050);
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PAINT ORANGE (3275 2050);
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DISPLAY INVISIBLE (3275 2050);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(3275 2050);
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DISPLAY 0.872340 (3275 2050);
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PAINT ORANGE (3275 2050);
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DISPLAY INVISIBLE (3275 2050);
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FORCEPROP 1 LAST PATH I16
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J 0
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(2950 2225);
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DISPLAY 0.872340 (2950 2225);
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PAINT PINK (2950 2225);
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DISPLAY INVISIBLE (2950 2225);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(2950 2175);
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DISPLAY INVISIBLE (2950 2175);
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FORCEADD OUTPORT..1
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(2950 2125);
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FORCEPROP 1 LASTPIN (2900 2125) VHDL_PORT OUT
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J 0
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(2915 2055);
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DISPLAY 0.872340 (2915 2055);
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PAINT PINK (2915 2055);
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DISPLAY INVISIBLE (2915 2055);
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FORCEPROP 1 LASTPIN (2900 2125) HDL_PORT OUT
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J 0
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(3275 2000);
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DISPLAY 0.872340 (3275 2000);
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PAINT ORANGE (3275 2000);
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DISPLAY INVISIBLE (3275 2000);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(3275 2000);
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DISPLAY 0.872340 (3275 2000);
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PAINT ORANGE (3275 2000);
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DISPLAY INVISIBLE (3275 2000);
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FORCEPROP 1 LAST PATH I17
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J 0
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(2950 2175);
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DISPLAY 0.872340 (2950 2175);
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PAINT PINK (2950 2175);
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DISPLAY INVISIBLE (2950 2175);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(2950 2125);
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DISPLAY INVISIBLE (2950 2125);
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FORCEADD OUTPORT..1
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(2875 1300);
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FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
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(3200 1175);
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DISPLAY 0.872340 (3200 1175);
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PAINT ORANGE (3200 1175);
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DISPLAY INVISIBLE (3200 1175);
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FORCEPROP 1 LASTPIN (2825 1300) HDL_PORT OUT
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J 0
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(3200 1175);
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DISPLAY 0.872340 (3200 1175);
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PAINT ORANGE (3200 1175);
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DISPLAY INVISIBLE (3200 1175);
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FORCEPROP 1 LASTPIN (2825 1300) VHDL_PORT OUT
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J 0
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(2840 1230);
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DISPLAY 0.872340 (2840 1230);
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PAINT PINK (2840 1230);
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DISPLAY INVISIBLE (2840 1230);
|
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FORCEPROP 1 LAST PATH I18
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J 0
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(2875 1350);
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DISPLAY 0.872340 (2875 1350);
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PAINT PINK (2875 1350);
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DISPLAY INVISIBLE (2875 1350);
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FORCEPROP 2 LAST CDS_LIB standard
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J 0
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(2875 1300);
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DISPLAY INVISIBLE (2875 1300);
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FORCEADD RIBBON_DELAY..1
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(1425 2275);
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FORCEPROP 2 LAST PATH I2
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J 0
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(1775 2825);
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DISPLAY 1.021277 (1775 2825);
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PAINT ORANGE (1775 2825);
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FORCEPROP 1 LASTPIN (1925 2125) VHDL_MODE OUT
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J 0
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(1945 2058);
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DISPLAY INVISIBLE (1945 2058);
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FORCEPROP 1 LASTPIN (1925 2175) VHDL_MODE OUT
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J 0
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(1945 2108);
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DISPLAY INVISIBLE (1945 2108);
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FORCEPROP 1 LASTPIN (950 2450) VHDL_MODE IN
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J 2
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(930 2383);
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DISPLAY INVISIBLE (930 2383);
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FORCEPROP 1 LASTPIN (950 2550) VHDL_MODE IN
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J 2
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(930 2483);
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DISPLAY INVISIBLE (930 2483);
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FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 0
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(1425 2275);
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DISPLAY INVISIBLE (1425 2275);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(1425 2285);
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DISPLAY INVISIBLE (1425 2285);
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FORCEADD ECL_TRANSLATION..1
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(-2425 2750);
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FORCEPROP 2 LAST PATH I20
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J 0
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(-1850 3600);
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DISPLAY 1.021277 (-1850 3600);
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PAINT ORANGE (-1850 3600);
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FORCEPROP 1 LASTPIN (-1650 2275) VHDL_MODE OUT
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J 0
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(-1630 2208);
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DISPLAY INVISIBLE (-1630 2208);
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FORCEPROP 1 LASTPIN (-1650 2400) VHDL_MODE OUT
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J 0
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(-1630 2333);
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DISPLAY INVISIBLE (-1630 2333);
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FORCEPROP 1 LASTPIN (-1650 2450) VHDL_MODE OUT
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|
J 0
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(-1630 2383);
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DISPLAY INVISIBLE (-1630 2383);
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FORCEPROP 1 LASTPIN (-1650 2550) VHDL_MODE OUT
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J 0
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(-1630 2483);
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DISPLAY INVISIBLE (-1630 2483);
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FORCEPROP 1 LASTPIN (-1650 2950) VHDL_MODE OUT
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J 0
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(-1630 2883);
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DISPLAY INVISIBLE (-1630 2883);
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FORCEPROP 1 LASTPIN (-1650 3150) VHDL_MODE OUT
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J 0
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|
(-1630 3083);
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DISPLAY INVISIBLE (-1630 3083);
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FORCEPROP 1 LASTPIN (-1650 3350) VHDL_MODE OUT
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|
J 0
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(-1630 3283);
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DISPLAY INVISIBLE (-1630 3283);
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FORCEPROP 1 LASTPIN (-3200 3025) VHDL_MODE IN
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|
J 2
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(-3220 2958);
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DISPLAY INVISIBLE (-3220 2958);
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FORCEPROP 1 LASTPIN (-3200 3150) VHDL_MODE IN
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|
J 2
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|
(-3220 3083);
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DISPLAY INVISIBLE (-3220 3083);
|
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FORCEPROP 1 LASTPIN (-3200 3225) VHDL_MODE IN
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|
J 2
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(-3220 3158);
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DISPLAY INVISIBLE (-3220 3158);
|
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FORCEPROP 1 LASTPIN (-3200 3300) VHDL_MODE IN
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|
J 2
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|
(-3220 3233);
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DISPLAY INVISIBLE (-3220 3233);
|
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FORCEPROP 1 LASTPIN (-3200 2350) VHDL_MODE IN
|
|
J 2
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|
(-3220 2283);
|
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DISPLAY INVISIBLE (-3220 2283);
|
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FORCEPROP 1 LASTPIN (-3200 2450) VHDL_MODE IN
|
|
J 2
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|
(-3220 2383);
|
|
DISPLAY INVISIBLE (-3220 2383);
|
|
FORCEPROP 1 LASTPIN (-3200 2550) VHDL_MODE IN
|
|
J 2
|
|
(-3220 2483);
|
|
DISPLAY INVISIBLE (-3220 2483);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
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|
(-2425 2760);
|
|
DISPLAY INVISIBLE (-2425 2760);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-2425 2750);
|
|
DISPLAY INVISIBLE (-2425 2750);
|
|
FORCEADD INPORT..1
|
|
(-4125 3300);
|
|
FORCEPROP 1 LASTPIN (-4075 3300) VHDL_PORT IN
|
|
J 0
|
|
(-4060 3230);
|
|
DISPLAY 0.872340 (-4060 3230);
|
|
PAINT PINK (-4060 3230);
|
|
DISPLAY INVISIBLE (-4060 3230);
|
|
FORCEPROP 1 LASTPIN (-4075 3300) HDL_PORT IN
|
|
J 0
|
|
(-3800 3175);
|
|
DISPLAY 0.872340 (-3800 3175);
|
|
PAINT ORANGE (-3800 3175);
|
|
DISPLAY INVISIBLE (-3800 3175);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3800 3175);
|
|
DISPLAY 0.872340 (-3800 3175);
|
|
PAINT ORANGE (-3800 3175);
|
|
DISPLAY INVISIBLE (-3800 3175);
|
|
FORCEPROP 1 LAST PATH I21
|
|
J 0
|
|
(-4150 3350);
|
|
DISPLAY 0.872340 (-4150 3350);
|
|
PAINT PINK (-4150 3350);
|
|
DISPLAY INVISIBLE (-4150 3350);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4125 3300);
|
|
DISPLAY INVISIBLE (-4125 3300);
|
|
FORCEADD INPORT..1
|
|
(-4125 3225);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4125 3225);
|
|
DISPLAY INVISIBLE (-4125 3225);
|
|
FORCEPROP 1 LAST PATH I22
|
|
J 0
|
|
(-4150 3275);
|
|
DISPLAY 0.872340 (-4150 3275);
|
|
PAINT PINK (-4150 3275);
|
|
DISPLAY INVISIBLE (-4150 3275);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3800 3100);
|
|
DISPLAY 0.872340 (-3800 3100);
|
|
PAINT ORANGE (-3800 3100);
|
|
DISPLAY INVISIBLE (-3800 3100);
|
|
FORCEPROP 1 LASTPIN (-4075 3225) HDL_PORT IN
|
|
J 0
|
|
(-3800 3100);
|
|
DISPLAY 0.872340 (-3800 3100);
|
|
PAINT ORANGE (-3800 3100);
|
|
DISPLAY INVISIBLE (-3800 3100);
|
|
FORCEPROP 1 LASTPIN (-4075 3225) VHDL_PORT IN
|
|
J 0
|
|
(-4060 3155);
|
|
DISPLAY 0.872340 (-4060 3155);
|
|
PAINT PINK (-4060 3155);
|
|
DISPLAY INVISIBLE (-4060 3155);
|
|
FORCEADD INPORT..1
|
|
(-4125 3150);
|
|
FORCEPROP 1 LASTPIN (-4075 3150) VHDL_PORT IN
|
|
J 0
|
|
(-4060 3080);
|
|
DISPLAY 0.872340 (-4060 3080);
|
|
PAINT PINK (-4060 3080);
|
|
DISPLAY INVISIBLE (-4060 3080);
|
|
FORCEPROP 1 LASTPIN (-4075 3150) HDL_PORT IN
|
|
J 0
|
|
(-3800 3025);
|
|
DISPLAY 0.872340 (-3800 3025);
|
|
PAINT ORANGE (-3800 3025);
|
|
DISPLAY INVISIBLE (-3800 3025);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3800 3025);
|
|
DISPLAY 0.872340 (-3800 3025);
|
|
PAINT ORANGE (-3800 3025);
|
|
DISPLAY INVISIBLE (-3800 3025);
|
|
FORCEPROP 1 LAST PATH I23
|
|
J 0
|
|
(-4150 3200);
|
|
DISPLAY 0.872340 (-4150 3200);
|
|
PAINT PINK (-4150 3200);
|
|
DISPLAY INVISIBLE (-4150 3200);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4125 3150);
|
|
DISPLAY INVISIBLE (-4125 3150);
|
|
FORCEADD INPORT..1
|
|
(-4125 3025);
|
|
FORCEPROP 1 LASTPIN (-4075 3025) VHDL_PORT IN
|
|
J 0
|
|
(-4060 2955);
|
|
DISPLAY 0.872340 (-4060 2955);
|
|
PAINT PINK (-4060 2955);
|
|
DISPLAY INVISIBLE (-4060 2955);
|
|
FORCEPROP 1 LASTPIN (-4075 3025) HDL_PORT IN
|
|
J 0
|
|
(-3800 2900);
|
|
DISPLAY 0.872340 (-3800 2900);
|
|
PAINT ORANGE (-3800 2900);
|
|
DISPLAY INVISIBLE (-3800 2900);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3800 2900);
|
|
DISPLAY 0.872340 (-3800 2900);
|
|
PAINT ORANGE (-3800 2900);
|
|
DISPLAY INVISIBLE (-3800 2900);
|
|
FORCEPROP 1 LAST PATH I24
|
|
J 0
|
|
(-4150 3075);
|
|
DISPLAY 0.872340 (-4150 3075);
|
|
PAINT PINK (-4150 3075);
|
|
DISPLAY INVISIBLE (-4150 3075);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4125 3025);
|
|
DISPLAY INVISIBLE (-4125 3025);
|
|
FORCEADD INPORT..1
|
|
(-4100 2550);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4100 2550);
|
|
DISPLAY INVISIBLE (-4100 2550);
|
|
FORCEPROP 1 LAST PATH I25
|
|
J 0
|
|
(-4125 2600);
|
|
DISPLAY 0.872340 (-4125 2600);
|
|
PAINT PINK (-4125 2600);
|
|
DISPLAY INVISIBLE (-4125 2600);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3775 2425);
|
|
DISPLAY 0.872340 (-3775 2425);
|
|
PAINT ORANGE (-3775 2425);
|
|
DISPLAY INVISIBLE (-3775 2425);
|
|
FORCEPROP 1 LASTPIN (-4050 2550) HDL_PORT IN
|
|
J 0
|
|
(-3775 2425);
|
|
DISPLAY 0.872340 (-3775 2425);
|
|
PAINT ORANGE (-3775 2425);
|
|
DISPLAY INVISIBLE (-3775 2425);
|
|
FORCEPROP 1 LASTPIN (-4050 2550) VHDL_PORT IN
|
|
J 0
|
|
(-4035 2480);
|
|
DISPLAY 0.872340 (-4035 2480);
|
|
PAINT PINK (-4035 2480);
|
|
DISPLAY INVISIBLE (-4035 2480);
|
|
FORCEADD INPORT..1
|
|
(-4100 2350);
|
|
FORCEPROP 1 LASTPIN (-4050 2350) VHDL_PORT IN
|
|
J 0
|
|
(-4035 2280);
|
|
DISPLAY 0.872340 (-4035 2280);
|
|
PAINT PINK (-4035 2280);
|
|
DISPLAY INVISIBLE (-4035 2280);
|
|
FORCEPROP 1 LASTPIN (-4050 2350) HDL_PORT IN
|
|
J 0
|
|
(-3775 2225);
|
|
DISPLAY 0.872340 (-3775 2225);
|
|
PAINT ORANGE (-3775 2225);
|
|
DISPLAY INVISIBLE (-3775 2225);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3775 2225);
|
|
DISPLAY 0.872340 (-3775 2225);
|
|
PAINT ORANGE (-3775 2225);
|
|
DISPLAY INVISIBLE (-3775 2225);
|
|
FORCEPROP 1 LAST PATH I26
|
|
J 0
|
|
(-4125 2400);
|
|
DISPLAY 0.872340 (-4125 2400);
|
|
PAINT PINK (-4125 2400);
|
|
DISPLAY INVISIBLE (-4125 2400);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4100 2350);
|
|
DISPLAY INVISIBLE (-4100 2350);
|
|
FORCEADD INPORT..1
|
|
(-4100 2450);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4100 2450);
|
|
DISPLAY INVISIBLE (-4100 2450);
|
|
FORCEPROP 1 LAST PATH I27
|
|
J 0
|
|
(-4125 2500);
|
|
DISPLAY 0.872340 (-4125 2500);
|
|
PAINT PINK (-4125 2500);
|
|
DISPLAY INVISIBLE (-4125 2500);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3775 2325);
|
|
DISPLAY 0.872340 (-3775 2325);
|
|
PAINT ORANGE (-3775 2325);
|
|
DISPLAY INVISIBLE (-3775 2325);
|
|
FORCEPROP 1 LASTPIN (-4050 2450) HDL_PORT IN
|
|
J 0
|
|
(-3775 2325);
|
|
DISPLAY 0.872340 (-3775 2325);
|
|
PAINT ORANGE (-3775 2325);
|
|
DISPLAY INVISIBLE (-3775 2325);
|
|
FORCEPROP 1 LASTPIN (-4050 2450) VHDL_PORT IN
|
|
J 0
|
|
(-4035 2380);
|
|
DISPLAY 0.872340 (-4035 2380);
|
|
PAINT PINK (-4035 2380);
|
|
DISPLAY INVISIBLE (-4035 2380);
|
|
FORCEADD OUTPORT..1
|
|
(-675 3350);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-675 3350);
|
|
DISPLAY INVISIBLE (-675 3350);
|
|
FORCEPROP 1 LAST PATH I28
|
|
J 0
|
|
(-675 3400);
|
|
DISPLAY 0.872340 (-675 3400);
|
|
PAINT PINK (-675 3400);
|
|
DISPLAY INVISIBLE (-675 3400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-350 3225);
|
|
DISPLAY 0.872340 (-350 3225);
|
|
PAINT ORANGE (-350 3225);
|
|
DISPLAY INVISIBLE (-350 3225);
|
|
FORCEPROP 1 LASTPIN (-725 3350) HDL_PORT OUT
|
|
J 0
|
|
(-350 3225);
|
|
DISPLAY 0.872340 (-350 3225);
|
|
PAINT ORANGE (-350 3225);
|
|
DISPLAY INVISIBLE (-350 3225);
|
|
FORCEPROP 1 LASTPIN (-725 3350) VHDL_PORT OUT
|
|
J 0
|
|
(-710 3280);
|
|
DISPLAY 0.872340 (-710 3280);
|
|
PAINT PINK (-710 3280);
|
|
DISPLAY INVISIBLE (-710 3280);
|
|
FORCEADD OUTPORT..1
|
|
(-675 3175);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-675 3175);
|
|
DISPLAY INVISIBLE (-675 3175);
|
|
FORCEPROP 1 LAST PATH I30
|
|
J 0
|
|
(-675 3225);
|
|
DISPLAY 0.872340 (-675 3225);
|
|
PAINT PINK (-675 3225);
|
|
DISPLAY INVISIBLE (-675 3225);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-350 3050);
|
|
DISPLAY 0.872340 (-350 3050);
|
|
PAINT ORANGE (-350 3050);
|
|
DISPLAY INVISIBLE (-350 3050);
|
|
FORCEPROP 1 LASTPIN (-725 3175) HDL_PORT OUT
|
|
J 0
|
|
(-350 3050);
|
|
DISPLAY 0.872340 (-350 3050);
|
|
PAINT ORANGE (-350 3050);
|
|
DISPLAY INVISIBLE (-350 3050);
|
|
FORCEPROP 1 LASTPIN (-725 3175) VHDL_PORT OUT
|
|
J 0
|
|
(-710 3105);
|
|
DISPLAY 0.872340 (-710 3105);
|
|
PAINT PINK (-710 3105);
|
|
DISPLAY INVISIBLE (-710 3105);
|
|
FORCEADD OUTPORT..1
|
|
(-675 2950);
|
|
FORCEPROP 1 LASTPIN (-725 2950) VHDL_PORT OUT
|
|
J 0
|
|
(-710 2880);
|
|
DISPLAY 0.872340 (-710 2880);
|
|
PAINT PINK (-710 2880);
|
|
DISPLAY INVISIBLE (-710 2880);
|
|
FORCEPROP 1 LASTPIN (-725 2950) HDL_PORT OUT
|
|
J 0
|
|
(-350 2825);
|
|
DISPLAY 0.872340 (-350 2825);
|
|
PAINT ORANGE (-350 2825);
|
|
DISPLAY INVISIBLE (-350 2825);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-350 2825);
|
|
DISPLAY 0.872340 (-350 2825);
|
|
PAINT ORANGE (-350 2825);
|
|
DISPLAY INVISIBLE (-350 2825);
|
|
FORCEPROP 1 LAST PATH I32
|
|
J 0
|
|
(-675 3000);
|
|
DISPLAY 0.872340 (-675 3000);
|
|
PAINT PINK (-675 3000);
|
|
DISPLAY INVISIBLE (-675 3000);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-675 2950);
|
|
DISPLAY INVISIBLE (-675 2950);
|
|
FORCEADD OUTPORT..1
|
|
(-750 2550);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-750 2550);
|
|
DISPLAY INVISIBLE (-750 2550);
|
|
FORCEPROP 1 LAST PATH I33
|
|
J 0
|
|
(-750 2600);
|
|
DISPLAY 0.872340 (-750 2600);
|
|
PAINT PINK (-750 2600);
|
|
DISPLAY INVISIBLE (-750 2600);
|
|
FORCEPROP 1 LASTPIN (-800 2550) VHDL_PORT OUT
|
|
J 0
|
|
(-785 2480);
|
|
DISPLAY 0.872340 (-785 2480);
|
|
PAINT PINK (-785 2480);
|
|
DISPLAY INVISIBLE (-785 2480);
|
|
FORCEPROP 1 LASTPIN (-800 2550) HDL_PORT OUT
|
|
J 0
|
|
(-425 2425);
|
|
DISPLAY 0.872340 (-425 2425);
|
|
PAINT ORANGE (-425 2425);
|
|
DISPLAY INVISIBLE (-425 2425);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-425 2425);
|
|
DISPLAY 0.872340 (-425 2425);
|
|
PAINT ORANGE (-425 2425);
|
|
DISPLAY INVISIBLE (-425 2425);
|
|
FORCEADD OUTPORT..1
|
|
(-750 2450);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-750 2450);
|
|
DISPLAY INVISIBLE (-750 2450);
|
|
FORCEPROP 1 LAST PATH I34
|
|
J 0
|
|
(-750 2500);
|
|
DISPLAY 0.872340 (-750 2500);
|
|
PAINT PINK (-750 2500);
|
|
DISPLAY INVISIBLE (-750 2500);
|
|
FORCEPROP 1 LASTPIN (-800 2450) VHDL_PORT OUT
|
|
J 0
|
|
(-785 2380);
|
|
DISPLAY 0.872340 (-785 2380);
|
|
PAINT PINK (-785 2380);
|
|
DISPLAY INVISIBLE (-785 2380);
|
|
FORCEPROP 1 LASTPIN (-800 2450) HDL_PORT OUT
|
|
J 0
|
|
(-425 2325);
|
|
DISPLAY 0.872340 (-425 2325);
|
|
PAINT ORANGE (-425 2325);
|
|
DISPLAY INVISIBLE (-425 2325);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-425 2325);
|
|
DISPLAY 0.872340 (-425 2325);
|
|
PAINT ORANGE (-425 2325);
|
|
DISPLAY INVISIBLE (-425 2325);
|
|
FORCEADD OUTPORT..1
|
|
(-750 2400);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-750 2400);
|
|
DISPLAY INVISIBLE (-750 2400);
|
|
FORCEPROP 1 LAST PATH I35
|
|
J 0
|
|
(-750 2450);
|
|
DISPLAY 0.872340 (-750 2450);
|
|
PAINT PINK (-750 2450);
|
|
DISPLAY INVISIBLE (-750 2450);
|
|
FORCEPROP 1 LASTPIN (-800 2400) VHDL_PORT OUT
|
|
J 0
|
|
(-785 2330);
|
|
DISPLAY 0.872340 (-785 2330);
|
|
PAINT PINK (-785 2330);
|
|
DISPLAY INVISIBLE (-785 2330);
|
|
FORCEPROP 1 LASTPIN (-800 2400) HDL_PORT OUT
|
|
J 0
|
|
(-425 2275);
|
|
DISPLAY 0.872340 (-425 2275);
|
|
PAINT ORANGE (-425 2275);
|
|
DISPLAY INVISIBLE (-425 2275);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-425 2275);
|
|
DISPLAY 0.872340 (-425 2275);
|
|
PAINT ORANGE (-425 2275);
|
|
DISPLAY INVISIBLE (-425 2275);
|
|
FORCEADD OUTPORT..1
|
|
(-775 2275);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-775 2275);
|
|
DISPLAY INVISIBLE (-775 2275);
|
|
FORCEPROP 1 LAST PATH I36
|
|
J 0
|
|
(-775 2325);
|
|
DISPLAY 0.872340 (-775 2325);
|
|
PAINT PINK (-775 2325);
|
|
DISPLAY INVISIBLE (-775 2325);
|
|
FORCEPROP 1 LASTPIN (-825 2275) VHDL_PORT OUT
|
|
J 0
|
|
(-810 2205);
|
|
DISPLAY 0.872340 (-810 2205);
|
|
PAINT PINK (-810 2205);
|
|
DISPLAY INVISIBLE (-810 2205);
|
|
FORCEPROP 1 LASTPIN (-825 2275) HDL_PORT OUT
|
|
J 0
|
|
(-450 2150);
|
|
DISPLAY 0.872340 (-450 2150);
|
|
PAINT ORANGE (-450 2150);
|
|
DISPLAY INVISIBLE (-450 2150);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-450 2150);
|
|
DISPLAY 0.872340 (-450 2150);
|
|
PAINT ORANGE (-450 2150);
|
|
DISPLAY INVISIBLE (-450 2150);
|
|
FORCEADD GENERIC_DELAYS..1
|
|
(1400 3800);
|
|
FORCEPROP 2 LAST PATH I5
|
|
J 0
|
|
(1875 4400);
|
|
DISPLAY 1.021277 (1875 4400);
|
|
PAINT ORANGE (1875 4400);
|
|
FORCEPROP 1 LASTPIN (2025 3900) VHDL_MODE OUT
|
|
J 0
|
|
(2045 3833);
|
|
DISPLAY INVISIBLE (2045 3833);
|
|
FORCEPROP 1 LASTPIN (2025 4075) VHDL_MODE OUT
|
|
J 0
|
|
(2045 4008);
|
|
DISPLAY INVISIBLE (2045 4008);
|
|
FORCEPROP 1 LASTPIN (750 3950) VHDL_MODE IN
|
|
J 2
|
|
(730 3883);
|
|
DISPLAY INVISIBLE (730 3883);
|
|
FORCEPROP 1 LASTPIN (750 4050) VHDL_MODE IN
|
|
J 2
|
|
(730 3983);
|
|
DISPLAY INVISIBLE (730 3983);
|
|
FORCEPROP 1 LASTPIN (750 3550) VHDL_MODE IN
|
|
J 2
|
|
(730 3483);
|
|
DISPLAY INVISIBLE (730 3483);
|
|
FORCEPROP 1 LASTPIN (750 3625) VHDL_MODE IN
|
|
J 2
|
|
(730 3558);
|
|
DISPLAY INVISIBLE (730 3558);
|
|
FORCEPROP 1 LASTPIN (750 3725) VHDL_MODE IN
|
|
J 2
|
|
(730 3658);
|
|
DISPLAY INVISIBLE (730 3658);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(1400 3810);
|
|
DISPLAY INVISIBLE (1400 3810);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(1400 3800);
|
|
DISPLAY INVISIBLE (1400 3800);
|
|
FORCEADD INPORT..1
|
|
(-225 3725);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(100 3600);
|
|
DISPLAY 0.872340 (100 3600);
|
|
PAINT ORANGE (100 3600);
|
|
DISPLAY INVISIBLE (100 3600);
|
|
FORCEPROP 1 LASTPIN (-175 3725) HDL_PORT IN
|
|
J 0
|
|
(100 3600);
|
|
DISPLAY 0.872340 (100 3600);
|
|
PAINT ORANGE (100 3600);
|
|
DISPLAY INVISIBLE (100 3600);
|
|
FORCEPROP 1 LASTPIN (-175 3725) VHDL_PORT IN
|
|
J 0
|
|
(-160 3655);
|
|
DISPLAY 0.872340 (-160 3655);
|
|
PAINT PINK (-160 3655);
|
|
DISPLAY INVISIBLE (-160 3655);
|
|
FORCEPROP 1 LAST PATH I6
|
|
J 0
|
|
(-250 3775);
|
|
DISPLAY 0.872340 (-250 3775);
|
|
PAINT PINK (-250 3775);
|
|
DISPLAY INVISIBLE (-250 3775);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-225 3725);
|
|
DISPLAY INVISIBLE (-225 3725);
|
|
FORCEADD INPORT..1
|
|
(-225 3625);
|
|
FORCEPROP 1 LASTPIN (-175 3625) VHDL_PORT IN
|
|
J 0
|
|
(-160 3555);
|
|
DISPLAY 0.872340 (-160 3555);
|
|
PAINT PINK (-160 3555);
|
|
DISPLAY INVISIBLE (-160 3555);
|
|
FORCEPROP 1 LASTPIN (-175 3625) HDL_PORT IN
|
|
J 0
|
|
(100 3500);
|
|
DISPLAY 0.872340 (100 3500);
|
|
PAINT ORANGE (100 3500);
|
|
DISPLAY INVISIBLE (100 3500);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(100 3500);
|
|
DISPLAY 0.872340 (100 3500);
|
|
PAINT ORANGE (100 3500);
|
|
DISPLAY INVISIBLE (100 3500);
|
|
FORCEPROP 1 LAST PATH I7
|
|
J 0
|
|
(-250 3675);
|
|
DISPLAY 0.872340 (-250 3675);
|
|
PAINT PINK (-250 3675);
|
|
DISPLAY INVISIBLE (-250 3675);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-225 3625);
|
|
DISPLAY INVISIBLE (-225 3625);
|
|
FORCEADD INPORT..1
|
|
(-225 3550);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-225 3550);
|
|
DISPLAY INVISIBLE (-225 3550);
|
|
FORCEPROP 1 LAST PATH I8
|
|
J 0
|
|
(-250 3600);
|
|
DISPLAY 0.872340 (-250 3600);
|
|
PAINT PINK (-250 3600);
|
|
DISPLAY INVISIBLE (-250 3600);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(100 3425);
|
|
DISPLAY 0.872340 (100 3425);
|
|
PAINT ORANGE (100 3425);
|
|
DISPLAY INVISIBLE (100 3425);
|
|
FORCEPROP 1 LASTPIN (-175 3550) HDL_PORT IN
|
|
J 0
|
|
(100 3425);
|
|
DISPLAY 0.872340 (100 3425);
|
|
PAINT ORANGE (100 3425);
|
|
DISPLAY INVISIBLE (100 3425);
|
|
FORCEPROP 1 LASTPIN (-175 3550) VHDL_PORT IN
|
|
J 0
|
|
(-160 3480);
|
|
DISPLAY 0.872340 (-160 3480);
|
|
PAINT PINK (-160 3480);
|
|
DISPLAY INVISIBLE (-160 3480);
|
|
FORCEADD INPORT..1
|
|
(-450 1400);
|
|
FORCEPROP 1 LASTPIN (-400 1400) VHDL_PORT IN
|
|
J 0
|
|
(-385 1330);
|
|
DISPLAY 0.872340 (-385 1330);
|
|
PAINT PINK (-385 1330);
|
|
DISPLAY INVISIBLE (-385 1330);
|
|
FORCEPROP 1 LASTPIN (-400 1400) HDL_PORT IN
|
|
J 0
|
|
(-125 1275);
|
|
DISPLAY 0.872340 (-125 1275);
|
|
PAINT ORANGE (-125 1275);
|
|
DISPLAY INVISIBLE (-125 1275);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-125 1275);
|
|
DISPLAY 0.872340 (-125 1275);
|
|
PAINT ORANGE (-125 1275);
|
|
DISPLAY INVISIBLE (-125 1275);
|
|
FORCEPROP 1 LAST PATH I9
|
|
J 0
|
|
(-475 1450);
|
|
DISPLAY 0.872340 (-475 1450);
|
|
PAINT PINK (-475 1450);
|
|
DISPLAY INVISIBLE (-475 1450);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-450 1400);
|
|
DISPLAY INVISIBLE (-450 1400);
|
|
FORCEADD PENN B SIZE PAGE..1
|
|
(3650 50);
|
|
FORCEPROP 2 LAST CDS_LIB misc
|
|
J 0
|
|
(3650 50);
|
|
DISPLAY INVISIBLE (3650 50);
|
|
FORCEPROP 1 LAST COMMENT_BODY TRUE
|
|
J 0
|
|
(1825 -25);
|
|
DISPLAY 0.872340 (1825 -25);
|
|
PAINT WHITE (1825 -25);
|
|
DISPLAY INVISIBLE (1825 -25);
|
|
WIRE 16 -1 (-1650 3175)(-725 3175);
|
|
FORCEPROP 2 LAST SIG_NAME LVDS_TO_ECL_OUT
|
|
J 0
|
|
(-1535 3210);
|
|
DISPLAY 1.021277 (-1535 3210);
|
|
PAINT ORANGE (-1535 3210);
|
|
WIRE 16 -1 (-1650 3150)(-1650 3175);
|
|
WIRE 16 -1 (-1650 3350)(-725 3350);
|
|
FORCEPROP 2 LAST SIG_NAME TTL_TO_ECL_OUT
|
|
J 0
|
|
(-1535 3360);
|
|
DISPLAY 1.021277 (-1535 3360);
|
|
PAINT ORANGE (-1535 3360);
|
|
WIRE 16 -1 (-3200 3025)(-4075 3025);
|
|
FORCEPROP 2 LAST SIG_NAME NIM_TO_ECL_IN
|
|
J 0
|
|
(-4035 3035);
|
|
DISPLAY 1.021277 (-4035 3035);
|
|
PAINT ORANGE (-4035 3035);
|
|
WIRE 16 -1 (-4075 3150)(-3200 3150);
|
|
FORCEPROP 2 LAST SIG_NAME LVDS_TO_ECL_IN_N
|
|
J 0
|
|
(-4035 3160);
|
|
DISPLAY 1.021277 (-4035 3160);
|
|
PAINT ORANGE (-4035 3160);
|
|
WIRE 16 -1 (-3200 3225)(-4075 3225);
|
|
FORCEPROP 2 LAST SIG_NAME LVDS_TO_ECL_IN_P
|
|
J 0
|
|
(-4010 3260);
|
|
DISPLAY 1.021277 (-4010 3260);
|
|
PAINT ORANGE (-4010 3260);
|
|
WIRE 16 -1 (-4075 3300)(-3200 3300);
|
|
FORCEPROP 2 LAST SIG_NAME TTL_TO_ECL_IN
|
|
J 0
|
|
(-3985 3335);
|
|
DISPLAY 1.021277 (-3985 3335);
|
|
PAINT ORANGE (-3985 3335);
|
|
WIRE 16 -1 (-4050 2350)(-3200 2350);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_NIM_IN
|
|
J 0
|
|
(-3985 2385);
|
|
DISPLAY 1.021277 (-3985 2385);
|
|
PAINT ORANGE (-3985 2385);
|
|
WIRE 16 -1 (-4050 2450)(-3200 2450);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_LVDS_IN
|
|
J 0
|
|
(-3960 2460);
|
|
DISPLAY 1.021277 (-3960 2460);
|
|
PAINT ORANGE (-3960 2460);
|
|
WIRE 16 -1 (-4050 2550)(-3200 2550);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_TTL_IN
|
|
J 0
|
|
(-3960 2585);
|
|
DISPLAY 1.021277 (-3960 2585);
|
|
PAINT ORANGE (-3960 2585);
|
|
WIRE 16 -1 (-1650 2950)(-725 2950);
|
|
FORCEPROP 2 LAST SIG_NAME NIM_TO_ECL_OUT
|
|
J 0
|
|
(-1560 2985);
|
|
DISPLAY 1.021277 (-1560 2985);
|
|
PAINT ORANGE (-1560 2985);
|
|
WIRE 16 -1 (-800 2550)(-1650 2550);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_TTL_OUT
|
|
J 0
|
|
(-1560 2585);
|
|
DISPLAY 1.021277 (-1560 2585);
|
|
PAINT ORANGE (-1560 2585);
|
|
WIRE 16 -1 (-1650 2450)(-800 2450);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_LVDS_OUT_P
|
|
J 0
|
|
(-1560 2485);
|
|
DISPLAY 1.021277 (-1560 2485);
|
|
PAINT ORANGE (-1560 2485);
|
|
WIRE 16 -1 (-800 2400)(-1650 2400);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_LVDS_OUT_N
|
|
J 0
|
|
(-1585 2410);
|
|
DISPLAY 1.021277 (-1585 2410);
|
|
PAINT ORANGE (-1585 2410);
|
|
WIRE 16 -1 (-1650 2275)(-825 2275);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_NIM_OUT
|
|
J 0
|
|
(-1560 2285);
|
|
DISPLAY 1.021277 (-1560 2285);
|
|
PAINT ORANGE (-1560 2285);
|
|
WIRE 16 -1 (950 2550)(-350 2550);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_IN_P
|
|
J 0
|
|
(-285 2610);
|
|
DISPLAY 1.021277 (-285 2610);
|
|
PAINT ORANGE (-285 2610);
|
|
WIRE 16 -1 (-350 2450)(950 2450);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_IN_N
|
|
J 0
|
|
(-235 2485);
|
|
DISPLAY 1.021277 (-235 2485);
|
|
PAINT ORANGE (-235 2485);
|
|
WIRE 16 -1 (-175 3550)(750 3550);
|
|
FORCEPROP 2 LAST SIG_NAME LE
|
|
J 0
|
|
(40 3560);
|
|
DISPLAY 1.021277 (40 3560);
|
|
PAINT ORANGE (40 3560);
|
|
WIRE 16 -1 (-175 3625)(750 3625);
|
|
FORCEPROP 2 LAST SIG_NAME CLK
|
|
J 0
|
|
(15 3660);
|
|
DISPLAY 1.021277 (15 3660);
|
|
PAINT ORANGE (15 3660);
|
|
WIRE 16 -1 (-200 4050)(750 4050);
|
|
FORCEPROP 2 LAST SIG_NAME GENERIC_PULSE_IN
|
|
J 0
|
|
(-135 4085);
|
|
DISPLAY 1.021277 (-135 4085);
|
|
PAINT ORANGE (-135 4085);
|
|
WIRE 16 -1 (-175 3725)(750 3725);
|
|
FORCEPROP 2 LAST SIG_NAME DATA
|
|
J 0
|
|
(-35 3785);
|
|
DISPLAY 1.021277 (-35 3785);
|
|
PAINT ORANGE (-35 3785);
|
|
WIRE 16 -1 (-200 3950)(750 3950);
|
|
FORCEPROP 2 LAST SIG_NAME GENERIC_DELAY_IN
|
|
J 0
|
|
(-135 3985);
|
|
DISPLAY 1.021277 (-135 3985);
|
|
PAINT ORANGE (-135 3985);
|
|
WIRE 16 -1 (1025 1400)(-400 1400);
|
|
FORCEPROP 2 LAST SIG_NAME PULSE_INV_IN
|
|
J 0
|
|
(-335 1510);
|
|
DISPLAY 1.021277 (-335 1510);
|
|
PAINT ORANGE (-335 1510);
|
|
WIRE 16 -1 (2900 2125)(1925 2125);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_OUT_N
|
|
J 0
|
|
(2090 2135);
|
|
DISPLAY 1.021277 (2090 2135);
|
|
PAINT ORANGE (2090 2135);
|
|
WIRE 16 -1 (3200 3900)(2025 3900);
|
|
FORCEPROP 2 LAST SIG_NAME GENERIC_DELAY_OUT
|
|
J 0
|
|
(2215 3935);
|
|
DISPLAY 1.021277 (2215 3935);
|
|
PAINT ORANGE (2215 3935);
|
|
WIRE 16 -1 (1925 2175)(2900 2175);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_OUT_P
|
|
J 0
|
|
(2065 2210);
|
|
DISPLAY 1.021277 (2065 2210);
|
|
PAINT ORANGE (2065 2210);
|
|
WIRE 16 -1 (2025 4075)(3225 4075);
|
|
FORCEPROP 2 LAST SIG_NAME GENERIC_PULSE_OUT
|
|
J 0
|
|
(2240 4135);
|
|
DISPLAY 1.021277 (2240 4135);
|
|
PAINT ORANGE (2240 4135);
|
|
WIRE 16 -1 (1925 1300)(2825 1300);
|
|
FORCEPROP 2 LAST SIG_NAME PULSE_INV_OUT
|
|
J 0
|
|
(2065 1410);
|
|
DISPLAY 1.021277 (2065 1410);
|
|
PAINT ORANGE (2065 1410);
|
|
FORCENOTE
|
|
8D
|
|
(-2525 2950) 0;
|
|
DISPLAY LEFT (-2525 2950);
|
|
DISPLAY 1.021277 (-2525 2950);
|
|
PAINT PURPLE (-2525 2950);
|
|
FORCENOTE
|
|
8C
|
|
(1325 3950) 0;
|
|
DISPLAY LEFT (1325 3950);
|
|
DISPLAY 1.021277 (1325 3950);
|
|
PAINT PURPLE (1325 3950);
|
|
FORCENOTE
|
|
8B
|
|
(1425 2400) 0;
|
|
DISPLAY LEFT (1425 2400);
|
|
DISPLAY 1.021277 (1425 2400);
|
|
PAINT PURPLE (1425 2400);
|
|
FORCENOTE
|
|
8A
|
|
(1475 1500) 0;
|
|
DISPLAY LEFT (1475 1500);
|
|
DISPLAY 1.021277 (1475 1500);
|
|
PAINT PURPLE (1475 1500);
|
|
FORCENOTE
|
|
GENERAL UTILITIES
|
|
(-2775 4525) 0;
|
|
DISPLAY LEFT (-2775 4525);
|
|
DISPLAY 3.148936 (-2775 4525);
|
|
PAINT PURPLE (-2775 4525);
|
|
FORCENOTE
|
|
8
|
|
(3125 100) 0;
|
|
DISPLAY LEFT (3125 100);
|
|
DISPLAY 1.021277 (3125 100);
|
|
PAINT PURPLE (3125 100);
|
|
QUIT
|