19 lines
316 B
Verilog
19 lines
316 B
Verilog
// generated by newgenasym Sat Feb 28 21:06:58 2015
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module generic_delays (clk, data, delay_in, delay_out, le, pulse_in, pulse_out);
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input clk;
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input data;
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input delay_in;
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output delay_out;
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input le;
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input pulse_in;
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output pulse_out;
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initial
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begin
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end
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endmodule
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