16 lines
413 B
VHDL
16 lines
413 B
VHDL
-- generated by newgenasym Sat Feb 28 21:06:58 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity generic_delays is
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port (
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CLK: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DELAY_IN: IN STD_LOGIC;
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DELAY_OUT: OUT STD_LOGIC;
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LE: IN STD_LOGIC;
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PULSE_IN: IN STD_LOGIC;
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PULSE_OUT: OUT STD_LOGIC);
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end generic_delays;
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