21 lines
338 B
Verilog
21 lines
338 B
Verilog
// generated by newgenasym Thu Mar 05 15:16:05 2015
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module gt_delays (clk, data, ddgt_n, ddgt_p, dgt2, dgt_n, dgt_p, gt_ttl, le);
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input clk;
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input data;
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output ddgt_n;
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output ddgt_p;
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output dgt2;
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output dgt_n;
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output dgt_p;
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input gt_ttl;
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input le;
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initial
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begin
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end
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endmodule
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