18 lines
471 B
VHDL
18 lines
471 B
VHDL
-- generated by newgenasym Thu Mar 05 15:16:05 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity gt_delays is
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port (
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CLK: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DDGT_N: OUT STD_LOGIC;
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DDGT_P: OUT STD_LOGIC;
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DGT2: OUT STD_LOGIC;
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DGT_N: OUT STD_LOGIC;
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DGT_P: OUT STD_LOGIC;
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GT_TTL: IN STD_LOGIC;
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LE: IN STD_LOGIC);
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end gt_delays;
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