25 lines
462 B
Verilog
25 lines
462 B
Verilog
// generated by newgenasym Thu Mar 05 15:15:57 2015
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module lo_gen (clk, data, dgt2, dgt_n, dgt_p, gt_ttl, le, lo_sel, lo_star2,
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lo_star_out_n, lo_star_out_p, \mtcd_lo* );
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input clk;
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input data;
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output dgt2;
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output dgt_n;
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output dgt_p;
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input gt_ttl;
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input le;
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input lo_sel;
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output lo_star2;
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output lo_star_out_n;
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output lo_star_out_p;
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input \mtcd_lo* ;
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initial
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begin
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end
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endmodule
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