21 lines
576 B
VHDL
21 lines
576 B
VHDL
-- generated by newgenasym Thu Mar 05 15:15:58 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity lo_gen is
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port (
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CLK: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DGT2: OUT STD_LOGIC;
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DGT_N: OUT STD_LOGIC;
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DGT_P: OUT STD_LOGIC;
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GT_TTL: IN STD_LOGIC;
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LE: IN STD_LOGIC;
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LO_SEL: IN STD_LOGIC;
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LO_STAR2: OUT STD_LOGIC;
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LO_STAR_OUT_N: OUT STD_LOGIC;
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LO_STAR_OUT_P: OUT STD_LOGIC;
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\mtcd_lo*\: IN STD_LOGIC);
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end lo_gen;
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