53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
// generated by newgenasym Thu May 28 15:41:42 2015
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module microzed_module (bckp_clk_in_use, caen_data_rdy, clk, clk100_in,
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clocks_data_rdy, cntrl_rdy, cntrl_reg_chk, data, ext_trig,
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generic_delay_in, generic_delay_out, generic_pulse, gt,
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le, mtca_mimic_data_rdy, mtca_mimic_trig1,
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mtca_mimic_trig2, mux_enable, read_cntrl_reg_bit,
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reset_clk, scaler, smellie_delay, smellie_pre_delay,
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smellie_pulse, spkr, sync, sync24, tellie_delay,
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tellie_pre_delay, tellie_pulse, tubii_rt_out, unnused_mz,
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vcc_io_en);
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input bckp_clk_in_use;
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output caen_data_rdy;
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output clk;
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input clk100_in;
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output clocks_data_rdy;
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output cntrl_rdy;
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input cntrl_reg_chk;
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output data;
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input [0:15] ext_trig;
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input generic_delay_in;
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output generic_delay_out;
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output generic_pulse;
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input gt;
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output [2:0] le;
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output mtca_mimic_data_rdy;
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input mtca_mimic_trig1;
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input mtca_mimic_trig2;
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output mux_enable;
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output read_cntrl_reg_bit;
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output reset_clk;
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output [4:6] scaler;
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output smellie_delay;
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input smellie_pre_delay;
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output smellie_pulse;
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output spkr;
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input sync;
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input sync24;
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output tellie_delay;
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input tellie_pre_delay;
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output tellie_pulse;
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output tubii_rt_out;
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output [0:15] unnused_mz;
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output vcc_io_en;
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initial
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begin
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end
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endmodule
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