42 lines
1.4 KiB
VHDL
42 lines
1.4 KiB
VHDL
-- generated by newgenasym Thu May 28 15:41:42 2015
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity microzed_module is
|
|
port (
|
|
BCKP_CLK_IN_USE: IN STD_LOGIC;
|
|
CAEN_DATA_RDY: OUT STD_LOGIC;
|
|
CLK: OUT STD_LOGIC;
|
|
CLK100_IN: IN STD_LOGIC;
|
|
CLOCKS_DATA_RDY: OUT STD_LOGIC;
|
|
CNTRL_RDY: OUT STD_LOGIC;
|
|
CNTRL_REG_CHK: IN STD_LOGIC;
|
|
DATA: OUT STD_LOGIC;
|
|
EXT_TRIG: IN STD_LOGIC_VECTOR (0 TO 15);
|
|
GENERIC_DELAY_IN: IN STD_LOGIC;
|
|
GENERIC_DELAY_OUT: OUT STD_LOGIC;
|
|
GENERIC_PULSE: OUT STD_LOGIC;
|
|
GT: IN STD_LOGIC;
|
|
LE: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
|
|
MTCA_MIMIC_DATA_RDY: OUT STD_LOGIC;
|
|
MTCA_MIMIC_TRIG1: IN STD_LOGIC;
|
|
MTCA_MIMIC_TRIG2: IN STD_LOGIC;
|
|
MUX_ENABLE: OUT STD_LOGIC;
|
|
READ_CNTRL_REG_BIT: OUT STD_LOGIC;
|
|
RESET_CLK: OUT STD_LOGIC;
|
|
SCALER: OUT STD_LOGIC_VECTOR (4 TO 6);
|
|
SMELLIE_DELAY: OUT STD_LOGIC;
|
|
SMELLIE_PRE_DELAY: IN STD_LOGIC;
|
|
SMELLIE_PULSE: OUT STD_LOGIC;
|
|
SPKR: OUT STD_LOGIC;
|
|
SYNC: IN STD_LOGIC;
|
|
SYNC24: IN STD_LOGIC;
|
|
TELLIE_DELAY: OUT STD_LOGIC;
|
|
TELLIE_PRE_DELAY: IN STD_LOGIC;
|
|
TELLIE_PULSE: OUT STD_LOGIC;
|
|
TUBII_RT_OUT: OUT STD_LOGIC;
|
|
UNNUSED_MZ: OUT STD_LOGIC_VECTOR (0 TO 15);
|
|
VCC_IO_EN: OUT STD_LOGIC);
|
|
end microzed_module;
|