29 lines
596 B
Verilog
29 lines
596 B
Verilog
// generated by newgenasym Thu Apr 16 14:43:12 2015
|
|
|
|
|
|
module mtca_mimic (clk, data, data_rdy, dgt, gt, le, \lo* , pulse1_anal,
|
|
pulse2_anal, trig1_out_n, trig1_out_p, trig1_out_ttl,
|
|
trig2_out_n, trig2_out_p, trig2_out_ttl);
|
|
input clk;
|
|
input data;
|
|
input data_rdy;
|
|
input dgt;
|
|
input gt;
|
|
input le;
|
|
input \lo* ;
|
|
input pulse1_anal;
|
|
input pulse2_anal;
|
|
output trig1_out_n;
|
|
output trig1_out_p;
|
|
output trig1_out_ttl;
|
|
output trig2_out_n;
|
|
output trig2_out_p;
|
|
output trig2_out_ttl;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|