24 lines
697 B
VHDL
24 lines
697 B
VHDL
-- generated by newgenasym Thu Apr 16 14:43:12 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mtca_mimic is
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port (
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CLK: IN STD_LOGIC;
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DATA: IN STD_LOGIC;
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DATA_RDY: IN STD_LOGIC;
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DGT: IN STD_LOGIC;
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GT: IN STD_LOGIC;
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LE: IN STD_LOGIC;
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\lo*\: IN STD_LOGIC;
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PULSE1_ANAL: IN STD_LOGIC;
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PULSE2_ANAL: IN STD_LOGIC;
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TRIG1_OUT_N: OUT STD_LOGIC;
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TRIG1_OUT_P: OUT STD_LOGIC;
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TRIG1_OUT_TTL: OUT STD_LOGIC;
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TRIG2_OUT_N: OUT STD_LOGIC;
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TRIG2_OUT_P: OUT STD_LOGIC;
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TRIG2_OUT_TTL: OUT STD_LOGIC);
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end mtca_mimic;
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