Tubii_Tk2/worklib/power/entity/vhdl.vhd
2015-05-28 16:31:37 -04:00

10 lines
191 B
VHDL

-- generated by newgenasym Thu May 28 15:41:42 2015
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity power is
port (
VCC_IO_EN: IN STD_LOGIC);
end power;