14 lines
209 B
Verilog
14 lines
209 B
Verilog
// generated by newgenasym Sat Feb 28 19:11:40 2015
|
|
|
|
|
|
module pulse_inverter (pulse_inv_in, pulse_inv_out);
|
|
input pulse_inv_in;
|
|
output pulse_inv_out;
|
|
|
|
|
|
initial
|
|
begin
|
|
end
|
|
|
|
endmodule
|