11 lines
250 B
VHDL
11 lines
250 B
VHDL
-- generated by newgenasym Sat Feb 28 19:11:40 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity pulse_inverter is
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port (
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PULSE_INV_IN: IN STD_LOGIC;
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PULSE_INV_OUT: OUT STD_LOGIC);
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end pulse_inverter;
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