16 lines
270 B
Verilog
16 lines
270 B
Verilog
// generated by newgenasym Sat Feb 28 19:58:30 2015
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module ribbon_delay (pulse_in_n, pulse_in_p, pulse_out_n, pulse_out_p);
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input pulse_in_n;
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input pulse_in_p;
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output pulse_out_n;
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output pulse_out_p;
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initial
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begin
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end
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endmodule
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