19 lines
338 B
Verilog
19 lines
338 B
Verilog
// generated by newgenasym Sat Mar 07 19:13:05 2015
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module select_lo_src (\ddgt* , lo_sel, lo_star2, lo_star_out_n, lo_star_out_p,
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\mtcd_lo* );
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input \ddgt* ;
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input lo_sel;
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output lo_star2;
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output lo_star_out_n;
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output lo_star_out_p;
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input \mtcd_lo* ;
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initial
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begin
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end
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endmodule
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