22 lines
519 B
Verilog
22 lines
519 B
Verilog
// generated by newgenasym Wed Mar 04 19:06:10 2015
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module translation (ecl_to_lvds_out_n, ecl_to_lvds_out_p, ecl_to_nim_out,
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ecl_to_ttl_out, lvds_to_ecl_out_n, lvds_to_ecl_out_p,
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ttl_to_ecl_out_n, ttl_to_ecl_out_p);
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output ecl_to_lvds_out_n;
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output ecl_to_lvds_out_p;
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output ecl_to_nim_out;
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output ecl_to_ttl_out;
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output lvds_to_ecl_out_n;
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output lvds_to_ecl_out_p;
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output ttl_to_ecl_out_n;
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output ttl_to_ecl_out_p;
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initial
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begin
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end
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endmodule
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