17 lines
497 B
VHDL
17 lines
497 B
VHDL
-- generated by newgenasym Wed Mar 04 19:06:10 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity translation is
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port (
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ECL_TO_LVDS_OUT_N: OUT STD_LOGIC;
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ECL_TO_LVDS_OUT_P: OUT STD_LOGIC;
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ECL_TO_NIM_OUT: OUT STD_LOGIC;
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ECL_TO_TTL_OUT: OUT STD_LOGIC;
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LVDS_TO_ECL_OUT_N: OUT STD_LOGIC;
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LVDS_TO_ECL_OUT_P: OUT STD_LOGIC;
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TTL_TO_ECL_OUT_N: OUT STD_LOGIC;
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TTL_TO_ECL_OUT_P: OUT STD_LOGIC);
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end translation;
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