23 lines
734 B
VHDL
23 lines
734 B
VHDL
-- generated by newgenasym Fri Mar 06 14:04:58 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity translation_ports is
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port (
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ECL_TO_LVDS_IN: OUT STD_LOGIC;
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ECL_TO_LVDS_OUT_N: IN STD_LOGIC;
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ECL_TO_LVDS_OUT_P: IN STD_LOGIC;
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ECL_TO_NIM_IN: OUT STD_LOGIC;
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ECL_TO_NIM_OUT: IN STD_LOGIC;
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ECL_TO_TTL_IN: OUT STD_LOGIC;
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ECL_TO_TTL_OUT: IN STD_LOGIC;
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LVDS_TO_ECL_IN_N: OUT STD_LOGIC;
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LVDS_TO_ECL_IN_P: OUT STD_LOGIC;
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LVDS_TO_ECL_OUT: IN STD_LOGIC;
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NIM_TO_ECL_IN: OUT STD_LOGIC;
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NIM_TO_ECL_OUT: IN STD_LOGIC;
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TTL_TO_ECL_IN: OUT STD_LOGIC;
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TTL_TO_ECL_OUT: IN STD_LOGIC);
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end translation_ports;
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