32 lines
751 B
Verilog
32 lines
751 B
Verilog
// generated by newgenasym Thu Apr 16 14:38:18 2015
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module trigger_logic (dgt_gate, gt, \lo* , over_thresh1_n, over_thresh1_p,
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over_thresh2_n, over_thresh2_p, posneg1_n, posneg1_p,
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posneg2_n, posneg2_p, trig1_out_n, trig1_out_p,
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trig1_out_ttl, trig2_out_n, trig2_out_p, trig2_out_ttl);
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input dgt_gate;
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input gt;
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input \lo* ;
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input over_thresh1_n;
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input over_thresh1_p;
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input over_thresh2_n;
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input over_thresh2_p;
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input posneg1_n;
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input posneg1_p;
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input posneg2_n;
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input posneg2_p;
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output trig1_out_n;
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output trig1_out_p;
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output trig1_out_ttl;
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output trig2_out_n;
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output trig2_out_p;
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output trig2_out_ttl;
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initial
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begin
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end
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endmodule
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