26 lines
787 B
VHDL
26 lines
787 B
VHDL
-- generated by newgenasym Thu Apr 16 14:38:18 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity trigger_logic is
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port (
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DGT_GATE: IN STD_LOGIC;
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GT: IN STD_LOGIC;
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\lo*\: IN STD_LOGIC;
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OVER_THRESH1_N: IN STD_LOGIC;
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OVER_THRESH1_P: IN STD_LOGIC;
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OVER_THRESH2_N: IN STD_LOGIC;
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OVER_THRESH2_P: IN STD_LOGIC;
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POSNEG1_N: IN STD_LOGIC;
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POSNEG1_P: IN STD_LOGIC;
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POSNEG2_N: IN STD_LOGIC;
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POSNEG2_P: IN STD_LOGIC;
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TRIG1_OUT_N: OUT STD_LOGIC;
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TRIG1_OUT_P: OUT STD_LOGIC;
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TRIG1_OUT_TTL: OUT STD_LOGIC;
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TRIG2_OUT_N: OUT STD_LOGIC;
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TRIG2_OUT_P: OUT STD_LOGIC;
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TRIG2_OUT_TTL: OUT STD_LOGIC);
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end trigger_logic;
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