Tubii_Tk2/worklib/ttl_ecl/entity/verilog.v

18 lines
304 B
Verilog

// generated by newgenasym Wed Mar 04 11:59:35 2015
module ttl_ecl (ecl_in_n, ecl_in_p, ecl_out_n, ecl_out_p, ttl_in, ttl_out);
input ecl_in_n;
input ecl_in_p;
output ecl_out_n;
output ecl_out_p;
input ttl_in;
output ttl_out;
initial
begin
end
endmodule