15 lines
365 B
VHDL
15 lines
365 B
VHDL
-- generated by newgenasym Wed Mar 04 11:59:35 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity ttl_ecl is
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port (
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ECL_IN_N: IN STD_LOGIC;
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ECL_IN_P: IN STD_LOGIC;
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ECL_OUT_N: OUT STD_LOGIC;
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ECL_OUT_P: OUT STD_LOGIC;
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TTL_IN: IN STD_LOGIC;
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TTL_OUT: OUT STD_LOGIC);
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end ttl_ecl;
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