74 lines
2.7 KiB
VHDL
74 lines
2.7 KiB
VHDL
-- generated by newgenasym Thu May 28 01:16:03 2015
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity tubii_pcb is
|
|
port (
|
|
CAEN_OUT_ANAL: OUT STD_LOGIC_VECTOR (0 TO 7);
|
|
CLK100_N: OUT STD_LOGIC;
|
|
CLK100_P: OUT STD_LOGIC;
|
|
DGT_N: OUT STD_LOGIC;
|
|
DGT_P: OUT STD_LOGIC;
|
|
ECL_TO_LVDS_IN: IN STD_LOGIC;
|
|
ECL_TO_LVDS_OUT_N: OUT STD_LOGIC;
|
|
ECL_TO_LVDS_OUT_P: OUT STD_LOGIC;
|
|
ECL_TO_NIM_IN: IN STD_LOGIC;
|
|
ECL_TO_NIM_OUT: OUT STD_LOGIC;
|
|
ECL_TO_TTL_IN: IN STD_LOGIC;
|
|
ECL_TO_TTL_OUT: OUT STD_LOGIC;
|
|
EXT_PED_IN: IN STD_LOGIC;
|
|
EXT_PED_OUT: OUT STD_LOGIC;
|
|
EXT_TRIG_IN: IN STD_LOGIC_VECTOR (0 TO 15);
|
|
GENERIC_DELAY_IN: IN STD_LOGIC;
|
|
GENERIC_DELAY_OUT: OUT STD_LOGIC;
|
|
GENERIC_PULSE_OUT: OUT STD_LOGIC;
|
|
GT_N: IN STD_LOGIC;
|
|
GT_NIM: OUT STD_LOGIC;
|
|
GT_P: IN STD_LOGIC;
|
|
GT_TTL_OUT: OUT STD_LOGIC;
|
|
LO_STAR_OUT_N: OUT STD_LOGIC;
|
|
LO_STAR_OUT_P: OUT STD_LOGIC;
|
|
LVDS_TO_ECL_IN_N: IN STD_LOGIC;
|
|
LVDS_TO_ECL_IN_P: IN STD_LOGIC;
|
|
LVDS_TO_ECL_OUT: OUT STD_LOGIC;
|
|
MTCA_MIMI2_PULSE_ANAL: IN STD_LOGIC;
|
|
MTCA_MIMIC1_OUT_N: OUT STD_LOGIC;
|
|
MTCA_MIMIC1_OUT_P: OUT STD_LOGIC;
|
|
MTCA_MIMIC1_PULSE_ANAL: IN STD_LOGIC;
|
|
MTCA_MIMIC2_OUT_N: OUT STD_LOGIC;
|
|
MTCA_MIMIC2_OUT_P: OUT STD_LOGIC;
|
|
\mtcd_lo*\: IN STD_LOGIC;
|
|
NIM_TO_ECL_IN: IN STD_LOGIC;
|
|
NIM_TO_ECL_OUT: OUT STD_LOGIC;
|
|
PULSE_IN_ANAL: IN STD_LOGIC_VECTOR (0 TO 11);
|
|
PULSE_INV_IN: IN STD_LOGIC;
|
|
PULSE_INV_OUT: OUT STD_LOGIC;
|
|
RIBBON_PULSE_IN_N: IN STD_LOGIC;
|
|
RIBBON_PULSE_IN_P: IN STD_LOGIC;
|
|
RIBBON_PULSE_OUT_N: OUT STD_LOGIC;
|
|
RIBBON_PULSE_OUT_P: OUT STD_LOGIC;
|
|
SCALER: OUT STD_LOGIC_VECTOR (1 TO 6);
|
|
SCOPE_OUT_ANAL: OUT STD_LOGIC_VECTOR (0 TO 7);
|
|
SMELLIE_DELAY_IN: IN STD_LOGIC;
|
|
SMELLIE_DELAY_OUT: OUT STD_LOGIC;
|
|
SMELLIE_PULSE_OUT: OUT STD_LOGIC;
|
|
SYNC24_LVDS_N: OUT STD_LOGIC;
|
|
SYNC24_LVDS_P: OUT STD_LOGIC;
|
|
SYNC24_N: IN STD_LOGIC;
|
|
SYNC24_P: IN STD_LOGIC;
|
|
SYNC_LVDS_N: OUT STD_LOGIC;
|
|
SYNC_LVDS_P: OUT STD_LOGIC;
|
|
SYNC_N: IN STD_LOGIC;
|
|
SYNC_P: IN STD_LOGIC;
|
|
TELLIE_DELAY_IN: IN STD_LOGIC;
|
|
TELLIE_DELAY_OUT: OUT STD_LOGIC;
|
|
TELLIE_PULSE_OUT: OUT STD_LOGIC;
|
|
TTL_TO_ECL_IN: IN STD_LOGIC;
|
|
TTL_TO_ECL_OUT: OUT STD_LOGIC;
|
|
TUB_CLK_IN_N: IN STD_LOGIC;
|
|
TUB_CLK_IN_P: IN STD_LOGIC;
|
|
TUBII_RT_OUT: OUT STD_LOGIC;
|
|
UNNUSED_MZ: OUT STD_LOGIC_VECTOR (0 TO 15));
|
|
end tubii_pcb;
|