3916 lines
90 KiB
Plaintext
3916 lines
90 KiB
Plaintext
FILE_TYPE = MACRO_DRAWING;
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SET COLOR_WIRE YELLOW;
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SET COLOR_PROP MONO;
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SET COLOR_DOT WHITE;
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SET COLOR_ARC YELLOW;
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SET COLOR_BODY GREEN;
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SET COLOR_NOTE MONO;
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SET PROP_DISPLAY VALUE;
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SET PAGE_NUMBER P1;
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FORCEADD MICROZED_MODULE..1
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(-500 2775);
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FORCEPROP 2 LASTPIN (200 1725) SIG_NAME UN$1$MICROZEDMODULE$I1$MTCAMIMICTRIG2
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J 0
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(210 1735);
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DISPLAY 0.659574 (210 1735);
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PAINT MONO (210 1735);
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DISPLAY INVISIBLE (210 1735);
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FORCEPROP 2 LASTPIN (200 1800) SIG_NAME UN$1$MICROZEDMODULE$I1$MTCAMIMICTRIG1
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J 0
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(210 1810);
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DISPLAY 0.659574 (210 1810);
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PAINT MONO (210 1810);
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DISPLAY INVISIBLE (210 1810);
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FORCEPROP 2 LASTPIN (-1200 1825) SIG_NAME UN$1$MICROZEDMODULE$I1$MTCAMIMICDATARDY
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J 0
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(-1190 1835);
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DISPLAY 0.659574 (-1190 1835);
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PAINT MONO (-1190 1835);
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DISPLAY INVISIBLE (-1190 1835);
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FORCEPROP 2 LASTPIN (-1200 1725) SIG_NAME UN$1$MICROZEDMODULE$I1$VCCIOEN
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J 0
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(-1190 1735);
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DISPLAY 0.659574 (-1190 1735);
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PAINT MONO (-1190 1735);
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DISPLAY INVISIBLE (-1190 1735);
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FORCEPROP 2 LAST PATH I1
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J 0
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(50 4075);
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DISPLAY 1.021277 (50 4075);
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PAINT ORANGE (50 4075);
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FORCEPROP 1 LASTPIN (-1200 1725) VHDL_MODE OUT
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J 2
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(-1220 1658);
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DISPLAY INVISIBLE (-1220 1658);
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FORCEPROP 1 LASTPIN (200 2175) VHDL_MODE OUT
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J 0
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(220 2108);
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DISPLAY INVISIBLE (220 2108);
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FORCEPROP 1 LASTPIN (200 1725) VHDL_MODE IN
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J 0
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(220 1658);
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DISPLAY INVISIBLE (220 1658);
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FORCEPROP 1 LASTPIN (200 1800) VHDL_MODE IN
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J 0
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(220 1733);
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DISPLAY INVISIBLE (220 1733);
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FORCEPROP 1 LASTPIN (-1200 3475) VHDL_MODE OUT
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J 2
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(-1220 3408);
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DISPLAY INVISIBLE (-1220 3408);
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FORCEPROP 1 LASTPIN (200 1875) VHDL_MODE OUT
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J 0
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(220 1808);
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DISPLAY INVISIBLE (220 1808);
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FORCEPROP 1 LASTPIN (200 3000) VHDL_MODE IN
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J 0
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(220 2933);
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DISPLAY INVISIBLE (220 2933);
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FORCEPROP 1 LASTPIN (200 3050) VHDL_MODE IN
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J 0
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(220 2983);
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DISPLAY INVISIBLE (220 2983);
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FORCEPROP 1 LASTPIN (200 3100) VHDL_MODE IN
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J 0
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(220 3033);
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DISPLAY INVISIBLE (220 3033);
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FORCEPROP 1 LASTPIN (200 3375) VHDL_MODE IN
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J 0
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(220 3308);
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DISPLAY INVISIBLE (220 3308);
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FORCEPROP 1 LASTPIN (200 3475) VHDL_MODE IN
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J 0
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(220 3408);
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DISPLAY INVISIBLE (220 3408);
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FORCEPROP 1 LASTPIN (-1200 2000) VHDL_MODE IN
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J 2
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(-1220 1933);
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DISPLAY INVISIBLE (-1220 1933);
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FORCEPROP 1 LASTPIN (-1200 3650) VHDL_MODE OUT
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J 2
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(-1220 3583);
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DISPLAY INVISIBLE (-1220 3583);
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FORCEPROP 1 LASTPIN (-1200 3600) VHDL_MODE IN
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J 2
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(-1220 3533);
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DISPLAY INVISIBLE (-1220 3533);
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FORCEPROP 1 LASTPIN (200 3650) VHDL_MODE OUT
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J 0
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(220 3583);
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DISPLAY INVISIBLE (220 3583);
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FORCEPROP 1 LASTPIN (200 3750) VHDL_MODE IN
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J 0
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(220 3683);
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DISPLAY INVISIBLE (220 3683);
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FORCEPROP 1 LASTPIN (200 3850) VHDL_MODE OUT
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J 0
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(220 3783);
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DISPLAY INVISIBLE (220 3783);
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FORCEPROP 1 LASTPIN (-1200 1925) VHDL_MODE OUT
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J 2
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(-1220 1858);
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DISPLAY INVISIBLE (-1220 1858);
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FORCEPROP 1 LASTPIN (200 2850) VHDL_MODE OUT
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J 0
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(220 2783);
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DISPLAY INVISIBLE (220 2783);
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FORCEPROP 1 LASTPIN (200 2575) VHDL_MODE OUT
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J 0
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(220 2508);
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DISPLAY INVISIBLE (220 2508);
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FORCEPROP 1 LASTPIN (200 2700) VHDL_MODE OUT
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J 0
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(220 2633);
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DISPLAY INVISIBLE (220 2633);
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FORCEPROP 1 LASTPIN (200 2800) VHDL_MODE OUT
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J 0
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(220 2733);
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DISPLAY INVISIBLE (220 2733);
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FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 0
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(-500 2775);
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DISPLAY INVISIBLE (-500 2775);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(-500 2785);
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DISPLAY INVISIBLE (-500 2785);
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FORCEPROP 1 LASTPIN (-1200 3725) VHDL_MODE OUT
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J 2
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(-1220 3658);
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DISPLAY INVISIBLE (-1220 3658);
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FORCEPROP 1 LASTPIN (-1200 3800) VHDL_MODE OUT
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J 2
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(-1220 3733);
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DISPLAY INVISIBLE (-1220 3733);
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FORCEPROP 1 LASTPIN (-1200 3850) VHDL_MODE IN
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J 2
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(-1220 3783);
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DISPLAY INVISIBLE (-1220 3783);
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FORCEPROP 1 LASTPIN (200 2100) VHDL_MODE OUT
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J 0
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(220 2033);
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DISPLAY INVISIBLE (220 2033);
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FORCEPROP 1 LASTPIN (200 2000) VHDL_MODE OUT
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J 0
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(220 1933);
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DISPLAY INVISIBLE (220 1933);
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FORCEPROP 1 LASTPIN (-1200 1825) VHDL_MODE OUT
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J 2
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(-1220 1758);
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DISPLAY INVISIBLE (-1220 1758);
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FORCEPROP 1 LASTPIN (-1200 2100) VHDL_MODE OUT
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J 2
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(-1220 2033);
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DISPLAY INVISIBLE (-1220 2033);
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FORCEPROP 1 LASTPIN (-1200 3200) VHDL_MODE OUT
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J 2
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(-1220 3133);
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DISPLAY INVISIBLE (-1220 3133);
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FORCEPROP 1 LASTPIN (-1200 3275) VHDL_MODE OUT
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J 2
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(-1220 3208);
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DISPLAY INVISIBLE (-1220 3208);
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FORCEPROP 1 LASTPIN (-1200 3350) VHDL_MODE OUT
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J 2
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(-1220 3283);
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DISPLAY INVISIBLE (-1220 3283);
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FORCEPROP 1 LASTPIN (-1200 3425) VHDL_MODE OUT
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J 2
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(-1220 3358);
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DISPLAY INVISIBLE (-1220 3358);
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FORCEPROP 1 LASTPIN (-1200 3525) VHDL_MODE IN
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J 2
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(-1220 3458);
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DISPLAY INVISIBLE (-1220 3458);
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FORCEPROP 1 LASTPIN (-1200 2200) VHDL_MODE OUT
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J 2
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(-1220 2133);
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DISPLAY INVISIBLE (-1220 2133);
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FORCEADD CNTRL_REGISTER..1
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(1950 4325);
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FORCEPROP 2 LASTPIN (1350 4250) SIG_NAME UN$1$CNTRLREGISTER$I10$DATARDY
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J 0
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(1360 4260);
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DISPLAY 0.659574 (1360 4260);
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PAINT MONO (1360 4260);
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DISPLAY INVISIBLE (1360 4260);
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FORCEPROP 2 LASTPIN (2500 4025) SIG_NAME UN$1$CNTRLREGISTER$I10$REGVAL
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J 0
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(2510 4035);
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DISPLAY 0.659574 (2510 4035);
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PAINT MONO (2510 4035);
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DISPLAY INVISIBLE (2510 4035);
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FORCEPROP 2 LASTPIN (1350 4150) SIG_NAME UN$1$CNTRLREGISTER$I10$READBIT
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J 0
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(1360 4160);
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DISPLAY 0.659574 (1360 4160);
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PAINT MONO (1360 4160);
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DISPLAY INVISIBLE (1360 4160);
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FORCEPROP 2 LASTPIN (2500 4350) SIG_NAME UN$1$CNTRLREGISTER$I10$ECALENABLE
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J 0
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(2510 4360);
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DISPLAY 0.659574 (2510 4360);
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PAINT MONO (2510 4360);
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DISPLAY INVISIBLE (2510 4360);
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FORCEPROP 2 LASTPIN (2500 4450) SIG_NAME UN$1$CNTRLREGISTER$I10$LOSEL
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J 0
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(2510 4460);
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DISPLAY 0.659574 (2510 4460);
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PAINT MONO (2510 4460);
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DISPLAY INVISIBLE (2510 4460);
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FORCEPROP 2 LAST PATH I10
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J 0
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(2300 4875);
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DISPLAY 1.021277 (2300 4875);
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PAINT ORANGE (2300 4875);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(1950 4335);
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DISPLAY INVISIBLE (1950 4335);
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FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 0
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(1950 4325);
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DISPLAY INVISIBLE (1950 4325);
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FORCEPROP 1 LASTPIN (1350 4600) VHDL_MODE IN
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J 2
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(1330 4533);
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DISPLAY INVISIBLE (1330 4533);
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FORCEPROP 1 LASTPIN (1350 4475) VHDL_MODE IN
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J 2
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(1330 4408);
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DISPLAY INVISIBLE (1330 4408);
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FORCEPROP 1 LASTPIN (1350 4375) VHDL_MODE IN
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J 2
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(1330 4308);
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DISPLAY INVISIBLE (1330 4308);
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FORCEPROP 1 LASTPIN (1350 4150) VHDL_MODE IN
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J 2
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(1330 4083);
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DISPLAY INVISIBLE (1330 4083);
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FORCEPROP 1 LASTPIN (2500 4550) VHDL_MODE OUT
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J 0
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(2520 4483);
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DISPLAY INVISIBLE (2520 4483);
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FORCEPROP 1 LASTPIN (2500 4450) VHDL_MODE OUT
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J 0
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(2520 4383);
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DISPLAY INVISIBLE (2520 4383);
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FORCEPROP 1 LASTPIN (2500 4350) VHDL_MODE OUT
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J 0
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(2520 4283);
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DISPLAY INVISIBLE (2520 4283);
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FORCEPROP 1 LASTPIN (2500 4150) VHDL_MODE OUT
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J 0
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(2520 4083);
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DISPLAY INVISIBLE (2520 4083);
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FORCEPROP 1 LASTPIN (2500 4025) VHDL_MODE OUT
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J 0
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(2520 3958);
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DISPLAY INVISIBLE (2520 3958);
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FORCEPROP 1 LASTPIN (1350 4250) VHDL_MODE IN
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J 2
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(1330 4183);
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DISPLAY INVISIBLE (1330 4183);
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FORCEADD TUBII_SPKR..1
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R 2
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(-3100 300);
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FORCEPROP 2 LAST PATH I11
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J 2
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(-3250 700);
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DISPLAY 1.021277 (-3250 700);
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PAINT ORANGE (-3250 700);
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FORCEPROP 1 LASTPIN (-2700 350) VHDL_MODE IN
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|
J 0
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(-2680 283);
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DISPLAY INVISIBLE (-2680 283);
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|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 2
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(-3100 300);
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DISPLAY INVISIBLE (-3100 300);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(-3100 310);
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DISPLAY INVISIBLE (-3100 310);
|
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FORCEADD BASELINE_BUFFER..1
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(-3850 375);
|
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FORCEPROP 2 LAST PATH I12
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J 0
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(-3600 875);
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DISPLAY 1.021277 (-3600 875);
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PAINT ORANGE (-3600 875);
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FORCEPROP 1 LAST BLOCK TRUE
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J 1
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(-3850 385);
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DISPLAY INVISIBLE (-3850 385);
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FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
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J 0
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(-3850 375);
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DISPLAY INVISIBLE (-3850 375);
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FORCEADD LO_GEN..1
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(1875 2075);
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FORCEPROP 2 LASTPIN (2375 1975) SIG_NAME UN$1$LOGEN$I13$LOSTAR2
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J 0
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(2385 1985);
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DISPLAY 0.659574 (2385 1985);
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PAINT MONO (2385 1985);
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DISPLAY INVISIBLE (2385 1985);
|
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FORCEPROP 2 LAST PATH I13
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J 0
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(2175 2600);
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DISPLAY 1.021277 (2175 2600);
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PAINT ORANGE (2175 2600);
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FORCEPROP 1 LASTPIN (2375 1875) VHDL_MODE OUT
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J 0
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(2395 1808);
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DISPLAY INVISIBLE (2395 1808);
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FORCEPROP 1 LASTPIN (2375 2075) VHDL_MODE OUT
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|
J 0
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(2395 2008);
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DISPLAY INVISIBLE (2395 2008);
|
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FORCEPROP 1 LASTPIN (2375 2200) VHDL_MODE OUT
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|
J 0
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(2395 2133);
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DISPLAY INVISIBLE (2395 2133);
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FORCEPROP 1 LASTPIN (2375 2300) VHDL_MODE OUT
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|
J 0
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(2395 2233);
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DISPLAY INVISIBLE (2395 2233);
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FORCEPROP 1 LASTPIN (2375 2375) VHDL_MODE OUT
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J 0
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(2395 2308);
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DISPLAY INVISIBLE (2395 2308);
|
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FORCEPROP 1 LASTPIN (1375 1875) VHDL_MODE IN
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J 2
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(1355 1808);
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DISPLAY INVISIBLE (1355 1808);
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FORCEPROP 1 LASTPIN (1375 2025) VHDL_MODE IN
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J 2
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(1355 1958);
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DISPLAY INVISIBLE (1355 1958);
|
|
FORCEPROP 1 LASTPIN (1375 2100) VHDL_MODE IN
|
|
J 2
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|
(1355 2033);
|
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DISPLAY INVISIBLE (1355 2033);
|
|
FORCEPROP 1 LASTPIN (1375 2175) VHDL_MODE IN
|
|
J 2
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|
(1355 2108);
|
|
DISPLAY INVISIBLE (1355 2108);
|
|
FORCEPROP 1 LASTPIN (1375 2275) VHDL_MODE IN
|
|
J 2
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|
(1355 2208);
|
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DISPLAY INVISIBLE (1355 2208);
|
|
FORCEPROP 1 LASTPIN (1375 2375) VHDL_MODE IN
|
|
J 2
|
|
(1355 2308);
|
|
DISPLAY INVISIBLE (1355 2308);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
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|
(1875 2085);
|
|
DISPLAY INVISIBLE (1875 2085);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
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|
(1875 2075);
|
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DISPLAY INVISIBLE (1875 2075);
|
|
FORCEPROP 1 LASTPIN (2375 1975) VHDL_MODE OUT
|
|
J 0
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|
(2395 1908);
|
|
DISPLAY INVISIBLE (2395 1908);
|
|
FORCEPROP 2 LASTPIN (2375 1875) SIG_NAME UN$1$LOGEN$I13$DGT2
|
|
J 0
|
|
(2385 1885);
|
|
DISPLAY 0.659574 (2385 1885);
|
|
PAINT MONO (2385 1885);
|
|
DISPLAY INVISIBLE (2385 1885);
|
|
FORCEADD INPORT..1
|
|
(-4250 2750);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2750);
|
|
DISPLAY INVISIBLE (-4250 2750);
|
|
FORCEPROP 1 LAST PATH I14
|
|
J 0
|
|
(-4275 2800);
|
|
DISPLAY 0.872340 (-4275 2800);
|
|
PAINT PINK (-4275 2800);
|
|
DISPLAY INVISIBLE (-4275 2800);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2625);
|
|
DISPLAY 0.872340 (-3925 2625);
|
|
PAINT ORANGE (-3925 2625);
|
|
DISPLAY INVISIBLE (-3925 2625);
|
|
FORCEPROP 1 LASTPIN (-4200 2750) HDL_PORT IN
|
|
J 0
|
|
(-3925 2625);
|
|
DISPLAY 0.872340 (-3925 2625);
|
|
PAINT ORANGE (-3925 2625);
|
|
DISPLAY INVISIBLE (-3925 2625);
|
|
FORCEPROP 1 LASTPIN (-4200 2750) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2680);
|
|
DISPLAY 0.872340 (-4185 2680);
|
|
PAINT PINK (-4185 2680);
|
|
DISPLAY INVISIBLE (-4185 2680);
|
|
FORCEADD INPORT..1
|
|
(-4250 2675);
|
|
FORCEPROP 2 LASTPIN (-4200 2675) SIG_NAME LVDS_TO_ECL_IN_P
|
|
J 0
|
|
(-4210 2710);
|
|
DISPLAY 1.021277 (-4210 2710);
|
|
PAINT ORANGE (-4210 2710);
|
|
FORCEPROP 1 LASTPIN (-4200 2675) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2605);
|
|
DISPLAY 0.872340 (-4185 2605);
|
|
PAINT PINK (-4185 2605);
|
|
DISPLAY INVISIBLE (-4185 2605);
|
|
FORCEPROP 1 LASTPIN (-4200 2675) HDL_PORT IN
|
|
J 0
|
|
(-3925 2550);
|
|
DISPLAY 0.872340 (-3925 2550);
|
|
PAINT ORANGE (-3925 2550);
|
|
DISPLAY INVISIBLE (-3925 2550);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2550);
|
|
DISPLAY 0.872340 (-3925 2550);
|
|
PAINT ORANGE (-3925 2550);
|
|
DISPLAY INVISIBLE (-3925 2550);
|
|
FORCEPROP 1 LAST PATH I15
|
|
J 0
|
|
(-4275 2725);
|
|
DISPLAY 0.872340 (-4275 2725);
|
|
PAINT PINK (-4275 2725);
|
|
DISPLAY INVISIBLE (-4275 2725);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2675);
|
|
DISPLAY INVISIBLE (-4250 2675);
|
|
FORCEADD INPORT..1
|
|
(-4250 2625);
|
|
FORCEPROP 2 LASTPIN (-4200 2625) SIG_NAME LVDS_TO_ECL_IN_N
|
|
J 0
|
|
(-4185 2635);
|
|
DISPLAY 1.021277 (-4185 2635);
|
|
PAINT ORANGE (-4185 2635);
|
|
FORCEPROP 1 LASTPIN (-4200 2625) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2555);
|
|
DISPLAY 0.872340 (-4185 2555);
|
|
PAINT PINK (-4185 2555);
|
|
DISPLAY INVISIBLE (-4185 2555);
|
|
FORCEPROP 1 LASTPIN (-4200 2625) HDL_PORT IN
|
|
J 0
|
|
(-3925 2500);
|
|
DISPLAY 0.872340 (-3925 2500);
|
|
PAINT ORANGE (-3925 2500);
|
|
DISPLAY INVISIBLE (-3925 2500);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2500);
|
|
DISPLAY 0.872340 (-3925 2500);
|
|
PAINT ORANGE (-3925 2500);
|
|
DISPLAY INVISIBLE (-3925 2500);
|
|
FORCEPROP 1 LAST PATH I16
|
|
J 0
|
|
(-4275 2675);
|
|
DISPLAY 0.872340 (-4275 2675);
|
|
PAINT PINK (-4275 2675);
|
|
DISPLAY INVISIBLE (-4275 2675);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2625);
|
|
DISPLAY INVISIBLE (-4250 2625);
|
|
FORCEADD INPORT..1
|
|
(-4250 2525);
|
|
FORCEPROP 2 LASTPIN (-4200 2525) SIG_NAME NIM_TO_ECL_IN
|
|
J 0
|
|
(-4210 2560);
|
|
DISPLAY 1.021277 (-4210 2560);
|
|
PAINT ORANGE (-4210 2560);
|
|
FORCEPROP 1 LASTPIN (-4200 2525) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2455);
|
|
DISPLAY 0.872340 (-4185 2455);
|
|
PAINT PINK (-4185 2455);
|
|
DISPLAY INVISIBLE (-4185 2455);
|
|
FORCEPROP 1 LASTPIN (-4200 2525) HDL_PORT IN
|
|
J 0
|
|
(-3925 2400);
|
|
DISPLAY 0.872340 (-3925 2400);
|
|
PAINT ORANGE (-3925 2400);
|
|
DISPLAY INVISIBLE (-3925 2400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2400);
|
|
DISPLAY 0.872340 (-3925 2400);
|
|
PAINT ORANGE (-3925 2400);
|
|
DISPLAY INVISIBLE (-3925 2400);
|
|
FORCEPROP 1 LAST PATH I17
|
|
J 0
|
|
(-4275 2575);
|
|
DISPLAY 0.872340 (-4275 2575);
|
|
PAINT PINK (-4275 2575);
|
|
DISPLAY INVISIBLE (-4275 2575);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2525);
|
|
DISPLAY INVISIBLE (-4250 2525);
|
|
FORCEADD INPORT..1
|
|
(-4250 2450);
|
|
FORCEPROP 2 LASTPIN (-4200 2450) SIG_NAME ECL_TO_TTL_IN
|
|
J 0
|
|
(-4210 2485);
|
|
DISPLAY 1.021277 (-4210 2485);
|
|
PAINT ORANGE (-4210 2485);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2450);
|
|
DISPLAY INVISIBLE (-4250 2450);
|
|
FORCEPROP 1 LAST PATH I18
|
|
J 0
|
|
(-4275 2500);
|
|
DISPLAY 0.872340 (-4275 2500);
|
|
PAINT PINK (-4275 2500);
|
|
DISPLAY INVISIBLE (-4275 2500);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2325);
|
|
DISPLAY 0.872340 (-3925 2325);
|
|
PAINT ORANGE (-3925 2325);
|
|
DISPLAY INVISIBLE (-3925 2325);
|
|
FORCEPROP 1 LASTPIN (-4200 2450) HDL_PORT IN
|
|
J 0
|
|
(-3925 2325);
|
|
DISPLAY 0.872340 (-3925 2325);
|
|
PAINT ORANGE (-3925 2325);
|
|
DISPLAY INVISIBLE (-3925 2325);
|
|
FORCEPROP 1 LASTPIN (-4200 2450) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2380);
|
|
DISPLAY 0.872340 (-4185 2380);
|
|
PAINT PINK (-4185 2380);
|
|
DISPLAY INVISIBLE (-4185 2380);
|
|
FORCEADD INPORT..1
|
|
(-4250 2375);
|
|
FORCEPROP 2 LASTPIN (-4200 2375) SIG_NAME ECL_TO_LVDS_IN
|
|
J 0
|
|
(-4210 2410);
|
|
DISPLAY 1.021277 (-4210 2410);
|
|
PAINT ORANGE (-4210 2410);
|
|
FORCEPROP 1 LASTPIN (-4200 2375) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2305);
|
|
DISPLAY 0.872340 (-4185 2305);
|
|
PAINT PINK (-4185 2305);
|
|
DISPLAY INVISIBLE (-4185 2305);
|
|
FORCEPROP 1 LASTPIN (-4200 2375) HDL_PORT IN
|
|
J 0
|
|
(-3925 2250);
|
|
DISPLAY 0.872340 (-3925 2250);
|
|
PAINT ORANGE (-3925 2250);
|
|
DISPLAY INVISIBLE (-3925 2250);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2250);
|
|
DISPLAY 0.872340 (-3925 2250);
|
|
PAINT ORANGE (-3925 2250);
|
|
DISPLAY INVISIBLE (-3925 2250);
|
|
FORCEPROP 1 LAST PATH I19
|
|
J 0
|
|
(-4275 2425);
|
|
DISPLAY 0.872340 (-4275 2425);
|
|
PAINT PINK (-4275 2425);
|
|
DISPLAY INVISIBLE (-4275 2425);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2375);
|
|
DISPLAY INVISIBLE (-4250 2375);
|
|
FORCEADD CLOCKS..1
|
|
(-3050 4450);
|
|
FORCEPROP 2 LASTPIN (-2600 4325) SIG_NAME UN$1$CLOCKS$I2$BCKPUSED
|
|
J 0
|
|
(-2590 4335);
|
|
DISPLAY 0.659574 (-2590 4335);
|
|
PAINT MONO (-2590 4335);
|
|
DISPLAY INVISIBLE (-2590 4335);
|
|
FORCEPROP 2 LASTPIN (-3550 4650) SIG_NAME UN$1$CLOCKS$I2$DATARDY
|
|
J 0
|
|
(-3540 4660);
|
|
DISPLAY 0.659574 (-3540 4660);
|
|
PAINT MONO (-3540 4660);
|
|
DISPLAY INVISIBLE (-3540 4660);
|
|
FORCEPROP 2 LASTPIN (-2600 4425) SIG_NAME UN$1$CLOCKS$I2$CLK100TTL
|
|
J 0
|
|
(-2590 4435);
|
|
DISPLAY 0.659574 (-2590 4435);
|
|
PAINT MONO (-2590 4435);
|
|
DISPLAY INVISIBLE (-2590 4435);
|
|
FORCEPROP 2 LASTPIN (-3550 4700) SIG_NAME UN$1$CLOCKS$I2$CLKSEL
|
|
J 0
|
|
(-3540 4710);
|
|
DISPLAY 0.659574 (-3540 4710);
|
|
PAINT MONO (-3540 4710);
|
|
DISPLAY INVISIBLE (-3540 4710);
|
|
FORCEPROP 2 LAST PATH I2
|
|
J 0
|
|
(-2750 4900);
|
|
DISPLAY 1.021277 (-2750 4900);
|
|
PAINT ORANGE (-2750 4900);
|
|
FORCEPROP 1 LASTPIN (-3550 4250) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4183);
|
|
DISPLAY INVISIBLE (-3570 4183);
|
|
FORCEPROP 1 LASTPIN (-3550 4200) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4133);
|
|
DISPLAY INVISIBLE (-3570 4133);
|
|
FORCEPROP 1 LASTPIN (-3550 4500) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4433);
|
|
DISPLAY INVISIBLE (-3570 4433);
|
|
FORCEPROP 1 LASTPIN (-3550 4450) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4383);
|
|
DISPLAY INVISIBLE (-3570 4383);
|
|
FORCEPROP 1 LASTPIN (-3550 4575) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4508);
|
|
DISPLAY INVISIBLE (-3570 4508);
|
|
FORCEPROP 1 LASTPIN (-3550 4650) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4583);
|
|
DISPLAY INVISIBLE (-3570 4583);
|
|
FORCEPROP 1 LASTPIN (-3550 4700) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4633);
|
|
DISPLAY INVISIBLE (-3570 4633);
|
|
FORCEPROP 1 LASTPIN (-2600 4425) VHDL_MODE OUT
|
|
J 0
|
|
(-2580 4358);
|
|
DISPLAY INVISIBLE (-2580 4358);
|
|
FORCEPROP 1 LASTPIN (-2600 4525) VHDL_MODE OUT
|
|
J 0
|
|
(-2580 4458);
|
|
DISPLAY INVISIBLE (-2580 4458);
|
|
FORCEPROP 1 LASTPIN (-2600 4600) VHDL_MODE OUT
|
|
J 0
|
|
(-2580 4533);
|
|
DISPLAY INVISIBLE (-2580 4533);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-3050 4450);
|
|
DISPLAY INVISIBLE (-3050 4450);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(-3050 4460);
|
|
DISPLAY INVISIBLE (-3050 4460);
|
|
FORCEPROP 1 LASTPIN (-3550 4300) VHDL_MODE IN
|
|
J 2
|
|
(-3570 4233);
|
|
DISPLAY INVISIBLE (-3570 4233);
|
|
FORCEPROP 1 LASTPIN (-2600 4325) VHDL_MODE OUT
|
|
J 0
|
|
(-2580 4258);
|
|
DISPLAY INVISIBLE (-2580 4258);
|
|
FORCEPROP 2 LASTPIN (-3550 4200) SIG_NAME UN$1$CLOCKS$I2$RESET
|
|
J 0
|
|
(-3540 4210);
|
|
DISPLAY 0.659574 (-3540 4210);
|
|
PAINT MONO (-3540 4210);
|
|
DISPLAY INVISIBLE (-3540 4210);
|
|
FORCEADD INPORT..1
|
|
(-4250 2300);
|
|
FORCEPROP 2 LASTPIN (-4200 2300) SIG_NAME ECL_TO_NIM_IN
|
|
J 0
|
|
(-4185 2335);
|
|
DISPLAY 1.021277 (-4185 2335);
|
|
PAINT ORANGE (-4185 2335);
|
|
FORCEPROP 1 LASTPIN (-4200 2300) VHDL_PORT IN
|
|
J 0
|
|
(-4185 2230);
|
|
DISPLAY 0.872340 (-4185 2230);
|
|
PAINT PINK (-4185 2230);
|
|
DISPLAY INVISIBLE (-4185 2230);
|
|
FORCEPROP 1 LASTPIN (-4200 2300) HDL_PORT IN
|
|
J 0
|
|
(-3925 2175);
|
|
DISPLAY 0.872340 (-3925 2175);
|
|
PAINT ORANGE (-3925 2175);
|
|
DISPLAY INVISIBLE (-3925 2175);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3925 2175);
|
|
DISPLAY 0.872340 (-3925 2175);
|
|
PAINT ORANGE (-3925 2175);
|
|
DISPLAY INVISIBLE (-3925 2175);
|
|
FORCEPROP 1 LAST PATH I20
|
|
J 0
|
|
(-4275 2350);
|
|
DISPLAY 0.872340 (-4275 2350);
|
|
PAINT PINK (-4275 2350);
|
|
DISPLAY INVISIBLE (-4275 2350);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4250 2300);
|
|
DISPLAY INVISIBLE (-4250 2300);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2950);
|
|
FORCEPROP 1 LASTPIN (-1725 2950) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2880);
|
|
DISPLAY 0.872340 (-1710 2880);
|
|
PAINT PINK (-1710 2880);
|
|
DISPLAY INVISIBLE (-1710 2880);
|
|
FORCEPROP 1 LASTPIN (-1725 2950) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2825);
|
|
DISPLAY 0.872340 (-1350 2825);
|
|
PAINT ORANGE (-1350 2825);
|
|
DISPLAY INVISIBLE (-1350 2825);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2825);
|
|
DISPLAY 0.872340 (-1350 2825);
|
|
PAINT ORANGE (-1350 2825);
|
|
DISPLAY INVISIBLE (-1350 2825);
|
|
FORCEPROP 1 LAST PATH I21
|
|
J 0
|
|
(-1675 3000);
|
|
DISPLAY 0.872340 (-1675 3000);
|
|
PAINT PINK (-1675 3000);
|
|
DISPLAY INVISIBLE (-1675 3000);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2950);
|
|
DISPLAY INVISIBLE (-1675 2950);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2775);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2775);
|
|
DISPLAY INVISIBLE (-1675 2775);
|
|
FORCEPROP 1 LAST PATH I23
|
|
J 0
|
|
(-1675 2825);
|
|
DISPLAY 0.872340 (-1675 2825);
|
|
PAINT PINK (-1675 2825);
|
|
DISPLAY INVISIBLE (-1675 2825);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2650);
|
|
DISPLAY 0.872340 (-1350 2650);
|
|
PAINT ORANGE (-1350 2650);
|
|
DISPLAY INVISIBLE (-1350 2650);
|
|
FORCEPROP 1 LASTPIN (-1725 2775) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2650);
|
|
DISPLAY 0.872340 (-1350 2650);
|
|
PAINT ORANGE (-1350 2650);
|
|
DISPLAY INVISIBLE (-1350 2650);
|
|
FORCEPROP 1 LASTPIN (-1725 2775) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2705);
|
|
DISPLAY 0.872340 (-1710 2705);
|
|
PAINT PINK (-1710 2705);
|
|
DISPLAY INVISIBLE (-1710 2705);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2600);
|
|
FORCEPROP 1 LASTPIN (-1725 2600) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2530);
|
|
DISPLAY 0.872340 (-1710 2530);
|
|
PAINT PINK (-1710 2530);
|
|
DISPLAY INVISIBLE (-1710 2530);
|
|
FORCEPROP 1 LASTPIN (-1725 2600) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2475);
|
|
DISPLAY 0.872340 (-1350 2475);
|
|
PAINT ORANGE (-1350 2475);
|
|
DISPLAY INVISIBLE (-1350 2475);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2475);
|
|
DISPLAY 0.872340 (-1350 2475);
|
|
PAINT ORANGE (-1350 2475);
|
|
DISPLAY INVISIBLE (-1350 2475);
|
|
FORCEPROP 1 LAST PATH I25
|
|
J 0
|
|
(-1675 2650);
|
|
DISPLAY 0.872340 (-1675 2650);
|
|
PAINT PINK (-1675 2650);
|
|
DISPLAY INVISIBLE (-1675 2650);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2600);
|
|
DISPLAY INVISIBLE (-1675 2600);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2500);
|
|
FORCEPROP 1 LASTPIN (-1725 2500) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2430);
|
|
DISPLAY 0.872340 (-1710 2430);
|
|
PAINT PINK (-1710 2430);
|
|
DISPLAY INVISIBLE (-1710 2430);
|
|
FORCEPROP 1 LASTPIN (-1725 2500) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2375);
|
|
DISPLAY 0.872340 (-1350 2375);
|
|
PAINT ORANGE (-1350 2375);
|
|
DISPLAY INVISIBLE (-1350 2375);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2375);
|
|
DISPLAY 0.872340 (-1350 2375);
|
|
PAINT ORANGE (-1350 2375);
|
|
DISPLAY INVISIBLE (-1350 2375);
|
|
FORCEPROP 1 LAST PATH I26
|
|
J 0
|
|
(-1675 2550);
|
|
DISPLAY 0.872340 (-1675 2550);
|
|
PAINT PINK (-1675 2550);
|
|
DISPLAY INVISIBLE (-1675 2550);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2500);
|
|
DISPLAY INVISIBLE (-1675 2500);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2425);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2425);
|
|
DISPLAY INVISIBLE (-1675 2425);
|
|
FORCEPROP 1 LAST PATH I27
|
|
J 0
|
|
(-1675 2475);
|
|
DISPLAY 0.872340 (-1675 2475);
|
|
PAINT PINK (-1675 2475);
|
|
DISPLAY INVISIBLE (-1675 2475);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2300);
|
|
DISPLAY 0.872340 (-1350 2300);
|
|
PAINT ORANGE (-1350 2300);
|
|
DISPLAY INVISIBLE (-1350 2300);
|
|
FORCEPROP 1 LASTPIN (-1725 2425) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2300);
|
|
DISPLAY 0.872340 (-1350 2300);
|
|
PAINT ORANGE (-1350 2300);
|
|
DISPLAY INVISIBLE (-1350 2300);
|
|
FORCEPROP 1 LASTPIN (-1725 2425) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2355);
|
|
DISPLAY 0.872340 (-1710 2355);
|
|
PAINT PINK (-1710 2355);
|
|
DISPLAY INVISIBLE (-1710 2355);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2350);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2350);
|
|
DISPLAY INVISIBLE (-1675 2350);
|
|
FORCEPROP 1 LAST PATH I28
|
|
J 0
|
|
(-1675 2400);
|
|
DISPLAY 0.872340 (-1675 2400);
|
|
PAINT PINK (-1675 2400);
|
|
DISPLAY INVISIBLE (-1675 2400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2225);
|
|
DISPLAY 0.872340 (-1350 2225);
|
|
PAINT ORANGE (-1350 2225);
|
|
DISPLAY INVISIBLE (-1350 2225);
|
|
FORCEPROP 1 LASTPIN (-1725 2350) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2225);
|
|
DISPLAY 0.872340 (-1350 2225);
|
|
PAINT ORANGE (-1350 2225);
|
|
DISPLAY INVISIBLE (-1350 2225);
|
|
FORCEPROP 1 LASTPIN (-1725 2350) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2280);
|
|
DISPLAY 0.872340 (-1710 2280);
|
|
PAINT PINK (-1710 2280);
|
|
DISPLAY INVISIBLE (-1710 2280);
|
|
FORCEADD OUTPORT..1
|
|
(-1675 2275);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1675 2275);
|
|
DISPLAY INVISIBLE (-1675 2275);
|
|
FORCEPROP 1 LAST PATH I29
|
|
J 0
|
|
(-1675 2325);
|
|
DISPLAY 0.872340 (-1675 2325);
|
|
PAINT PINK (-1675 2325);
|
|
DISPLAY INVISIBLE (-1675 2325);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1350 2150);
|
|
DISPLAY 0.872340 (-1350 2150);
|
|
PAINT ORANGE (-1350 2150);
|
|
DISPLAY INVISIBLE (-1350 2150);
|
|
FORCEPROP 1 LASTPIN (-1725 2275) HDL_PORT OUT
|
|
J 0
|
|
(-1350 2150);
|
|
DISPLAY 0.872340 (-1350 2150);
|
|
PAINT ORANGE (-1350 2150);
|
|
DISPLAY INVISIBLE (-1350 2150);
|
|
FORCEPROP 1 LASTPIN (-1725 2275) VHDL_PORT OUT
|
|
J 0
|
|
(-1710 2205);
|
|
DISPLAY 0.872340 (-1710 2205);
|
|
PAINT PINK (-1710 2205);
|
|
DISPLAY INVISIBLE (-1710 2205);
|
|
FORCEADD MTCA_MIMIC..1
|
|
(-650 475);
|
|
FORCEPROP 2 LAST PATH I3
|
|
J 0
|
|
(-150 975);
|
|
DISPLAY 1.021277 (-150 975);
|
|
PAINT ORANGE (-150 975);
|
|
FORCEPROP 2 LASTPIN (0 625) SIG_NAME MTCA_MIMIC1_OUT_N
|
|
J 0
|
|
(-10 660);
|
|
DISPLAY 1.021277 (-10 660);
|
|
PAINT ORANGE (-10 660);
|
|
FORCEPROP 1 LASTPIN (0 825) VHDL_MODE OUT
|
|
J 0
|
|
(20 758);
|
|
DISPLAY INVISIBLE (20 758);
|
|
FORCEPROP 1 LASTPIN (0 925) VHDL_MODE OUT
|
|
J 0
|
|
(20 858);
|
|
DISPLAY INVISIBLE (20 858);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-650 475);
|
|
DISPLAY INVISIBLE (-650 475);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(-650 485);
|
|
DISPLAY INVISIBLE (-650 485);
|
|
FORCEPROP 1 LASTPIN (0 700) VHDL_MODE OUT
|
|
J 0
|
|
(20 633);
|
|
DISPLAY INVISIBLE (20 633);
|
|
FORCEPROP 1 LASTPIN (0 625) VHDL_MODE OUT
|
|
J 0
|
|
(20 558);
|
|
DISPLAY INVISIBLE (20 558);
|
|
FORCEPROP 1 LASTPIN (0 450) VHDL_MODE OUT
|
|
J 0
|
|
(20 383);
|
|
DISPLAY INVISIBLE (20 383);
|
|
FORCEPROP 1 LASTPIN (0 350) VHDL_MODE OUT
|
|
J 0
|
|
(20 283);
|
|
DISPLAY INVISIBLE (20 283);
|
|
FORCEPROP 1 LASTPIN (-1350 400) VHDL_MODE IN
|
|
J 2
|
|
(-1370 333);
|
|
DISPLAY INVISIBLE (-1370 333);
|
|
FORCEPROP 1 LASTPIN (-1350 325) VHDL_MODE IN
|
|
J 2
|
|
(-1370 258);
|
|
DISPLAY INVISIBLE (-1370 258);
|
|
FORCEPROP 1 LASTPIN (-1350 250) VHDL_MODE IN
|
|
J 2
|
|
(-1370 183);
|
|
DISPLAY INVISIBLE (-1370 183);
|
|
FORCEPROP 1 LASTPIN (-1350 1000) VHDL_MODE IN
|
|
J 2
|
|
(-1370 933);
|
|
DISPLAY INVISIBLE (-1370 933);
|
|
FORCEPROP 1 LASTPIN (-1350 875) VHDL_MODE IN
|
|
J 2
|
|
(-1370 808);
|
|
DISPLAY INVISIBLE (-1370 808);
|
|
FORCEPROP 1 LASTPIN (-1350 775) VHDL_MODE IN
|
|
J 2
|
|
(-1370 708);
|
|
DISPLAY INVISIBLE (-1370 708);
|
|
FORCEPROP 1 LASTPIN (-1350 700) VHDL_MODE IN
|
|
J 2
|
|
(-1370 633);
|
|
DISPLAY INVISIBLE (-1370 633);
|
|
FORCEPROP 1 LASTPIN (-1350 650) VHDL_MODE IN
|
|
J 2
|
|
(-1370 583);
|
|
DISPLAY INVISIBLE (-1370 583);
|
|
FORCEPROP 1 LASTPIN (-1350 575) VHDL_MODE IN
|
|
J 2
|
|
(-1370 508);
|
|
DISPLAY INVISIBLE (-1370 508);
|
|
FORCEADD INPORT..1
|
|
(-4225 2850);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4225 2850);
|
|
DISPLAY INVISIBLE (-4225 2850);
|
|
FORCEPROP 1 LAST PATH I30
|
|
J 0
|
|
(-4250 2900);
|
|
DISPLAY 0.872340 (-4250 2900);
|
|
PAINT PINK (-4250 2900);
|
|
DISPLAY INVISIBLE (-4250 2900);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3900 2725);
|
|
DISPLAY 0.872340 (-3900 2725);
|
|
PAINT ORANGE (-3900 2725);
|
|
DISPLAY INVISIBLE (-3900 2725);
|
|
FORCEPROP 1 LASTPIN (-4175 2850) HDL_PORT IN
|
|
J 0
|
|
(-3900 2725);
|
|
DISPLAY 0.872340 (-3900 2725);
|
|
PAINT ORANGE (-3900 2725);
|
|
DISPLAY INVISIBLE (-3900 2725);
|
|
FORCEPROP 1 LASTPIN (-4175 2850) VHDL_PORT IN
|
|
J 0
|
|
(-4160 2780);
|
|
DISPLAY 0.872340 (-4160 2780);
|
|
PAINT PINK (-4160 2780);
|
|
DISPLAY INVISIBLE (-4160 2780);
|
|
FORCEADD INPORT..1
|
|
(-4225 2900);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4225 2900);
|
|
DISPLAY INVISIBLE (-4225 2900);
|
|
FORCEPROP 1 LAST PATH I31
|
|
J 0
|
|
(-4250 2950);
|
|
DISPLAY 0.872340 (-4250 2950);
|
|
PAINT PINK (-4250 2950);
|
|
DISPLAY INVISIBLE (-4250 2950);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3900 2775);
|
|
DISPLAY 0.872340 (-3900 2775);
|
|
PAINT ORANGE (-3900 2775);
|
|
DISPLAY INVISIBLE (-3900 2775);
|
|
FORCEPROP 1 LASTPIN (-4175 2900) HDL_PORT IN
|
|
J 0
|
|
(-3900 2775);
|
|
DISPLAY 0.872340 (-3900 2775);
|
|
PAINT ORANGE (-3900 2775);
|
|
DISPLAY INVISIBLE (-3900 2775);
|
|
FORCEPROP 1 LASTPIN (-4175 2900) VHDL_PORT IN
|
|
J 0
|
|
(-4160 2830);
|
|
DISPLAY 0.872340 (-4160 2830);
|
|
PAINT PINK (-4160 2830);
|
|
DISPLAY INVISIBLE (-4160 2830);
|
|
FORCEADD INPORT..1
|
|
(-4225 2975);
|
|
FORCEPROP 2 LASTPIN (-4175 2975) SIG_NAME RIBBON_PULSE_IN_P
|
|
J 0
|
|
(-4160 3010);
|
|
DISPLAY 1.021277 (-4160 3010);
|
|
PAINT ORANGE (-4160 3010);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4225 2975);
|
|
DISPLAY INVISIBLE (-4225 2975);
|
|
FORCEPROP 1 LAST PATH I32
|
|
J 0
|
|
(-4250 3025);
|
|
DISPLAY 0.872340 (-4250 3025);
|
|
PAINT PINK (-4250 3025);
|
|
DISPLAY INVISIBLE (-4250 3025);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3900 2850);
|
|
DISPLAY 0.872340 (-3900 2850);
|
|
PAINT ORANGE (-3900 2850);
|
|
DISPLAY INVISIBLE (-3900 2850);
|
|
FORCEPROP 1 LASTPIN (-4175 2975) HDL_PORT IN
|
|
J 0
|
|
(-3900 2850);
|
|
DISPLAY 0.872340 (-3900 2850);
|
|
PAINT ORANGE (-3900 2850);
|
|
DISPLAY INVISIBLE (-3900 2850);
|
|
FORCEPROP 1 LASTPIN (-4175 2975) VHDL_PORT IN
|
|
J 0
|
|
(-4160 2905);
|
|
DISPLAY 0.872340 (-4160 2905);
|
|
PAINT PINK (-4160 2905);
|
|
DISPLAY INVISIBLE (-4160 2905);
|
|
FORCEADD INPORT..1
|
|
(-1800 3850);
|
|
FORCEPROP 2 LASTPIN (-1750 3850) SIG_NAME GENERIC_DELAY_IN
|
|
J 0
|
|
(-1735 3860);
|
|
DISPLAY 1.021277 (-1735 3860);
|
|
PAINT ORANGE (-1735 3860);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1800 3850);
|
|
DISPLAY INVISIBLE (-1800 3850);
|
|
FORCEPROP 1 LAST PATH I33
|
|
J 0
|
|
(-1825 3900);
|
|
DISPLAY 0.872340 (-1825 3900);
|
|
PAINT PINK (-1825 3900);
|
|
DISPLAY INVISIBLE (-1825 3900);
|
|
FORCEPROP 1 LASTPIN (-1750 3850) VHDL_PORT IN
|
|
J 0
|
|
(-1735 3780);
|
|
DISPLAY 0.872340 (-1735 3780);
|
|
PAINT PINK (-1735 3780);
|
|
DISPLAY INVISIBLE (-1735 3780);
|
|
FORCEPROP 1 LASTPIN (-1750 3850) HDL_PORT IN
|
|
J 0
|
|
(-1475 3725);
|
|
DISPLAY 0.872340 (-1475 3725);
|
|
PAINT ORANGE (-1475 3725);
|
|
DISPLAY INVISIBLE (-1475 3725);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1475 3725);
|
|
DISPLAY 0.872340 (-1475 3725);
|
|
PAINT ORANGE (-1475 3725);
|
|
DISPLAY INVISIBLE (-1475 3725);
|
|
FORCEADD OUTPORT..1
|
|
(-1650 3125);
|
|
FORCEPROP 1 LASTPIN (-1700 3125) VHDL_PORT OUT
|
|
J 0
|
|
(-1685 3055);
|
|
DISPLAY 0.872340 (-1685 3055);
|
|
PAINT PINK (-1685 3055);
|
|
DISPLAY INVISIBLE (-1685 3055);
|
|
FORCEPROP 1 LASTPIN (-1700 3125) HDL_PORT OUT
|
|
J 0
|
|
(-1325 3000);
|
|
DISPLAY 0.872340 (-1325 3000);
|
|
PAINT ORANGE (-1325 3000);
|
|
DISPLAY INVISIBLE (-1325 3000);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1325 3000);
|
|
DISPLAY 0.872340 (-1325 3000);
|
|
PAINT ORANGE (-1325 3000);
|
|
DISPLAY INVISIBLE (-1325 3000);
|
|
FORCEPROP 1 LAST PATH I34
|
|
J 0
|
|
(-1650 3175);
|
|
DISPLAY 0.872340 (-1650 3175);
|
|
PAINT PINK (-1650 3175);
|
|
DISPLAY INVISIBLE (-1650 3175);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1650 3125);
|
|
DISPLAY INVISIBLE (-1650 3125);
|
|
FORCEADD OUTPORT..1
|
|
(-1650 3225);
|
|
FORCEPROP 1 LASTPIN (-1700 3225) VHDL_PORT OUT
|
|
J 0
|
|
(-1685 3155);
|
|
DISPLAY 0.872340 (-1685 3155);
|
|
PAINT PINK (-1685 3155);
|
|
DISPLAY INVISIBLE (-1685 3155);
|
|
FORCEPROP 1 LASTPIN (-1700 3225) HDL_PORT OUT
|
|
J 0
|
|
(-1325 3100);
|
|
DISPLAY 0.872340 (-1325 3100);
|
|
PAINT ORANGE (-1325 3100);
|
|
DISPLAY INVISIBLE (-1325 3100);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1325 3100);
|
|
DISPLAY 0.872340 (-1325 3100);
|
|
PAINT ORANGE (-1325 3100);
|
|
DISPLAY INVISIBLE (-1325 3100);
|
|
FORCEPROP 1 LAST PATH I35
|
|
J 0
|
|
(-1650 3275);
|
|
DISPLAY 0.872340 (-1650 3275);
|
|
PAINT PINK (-1650 3275);
|
|
DISPLAY INVISIBLE (-1650 3275);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1650 3225);
|
|
DISPLAY INVISIBLE (-1650 3225);
|
|
FORCEADD OUTPORT..1
|
|
(-1650 3325);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1325 3200);
|
|
DISPLAY 0.872340 (-1325 3200);
|
|
PAINT ORANGE (-1325 3200);
|
|
DISPLAY INVISIBLE (-1325 3200);
|
|
FORCEPROP 1 LASTPIN (-1700 3325) HDL_PORT OUT
|
|
J 0
|
|
(-1325 3200);
|
|
DISPLAY 0.872340 (-1325 3200);
|
|
PAINT ORANGE (-1325 3200);
|
|
DISPLAY INVISIBLE (-1325 3200);
|
|
FORCEPROP 1 LASTPIN (-1700 3325) VHDL_PORT OUT
|
|
J 0
|
|
(-1685 3255);
|
|
DISPLAY 0.872340 (-1685 3255);
|
|
PAINT PINK (-1685 3255);
|
|
DISPLAY INVISIBLE (-1685 3255);
|
|
FORCEPROP 1 LAST PATH I36
|
|
J 0
|
|
(-1650 3375);
|
|
DISPLAY 0.872340 (-1650 3375);
|
|
PAINT PINK (-1650 3375);
|
|
DISPLAY INVISIBLE (-1650 3375);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1650 3325);
|
|
DISPLAY INVISIBLE (-1650 3325);
|
|
FORCEADD OUTPORT..1
|
|
(-1650 3400);
|
|
FORCEPROP 1 LASTPIN (-1700 3400) VHDL_PORT OUT
|
|
J 0
|
|
(-1685 3330);
|
|
DISPLAY 0.872340 (-1685 3330);
|
|
PAINT PINK (-1685 3330);
|
|
DISPLAY INVISIBLE (-1685 3330);
|
|
FORCEPROP 1 LASTPIN (-1700 3400) HDL_PORT OUT
|
|
J 0
|
|
(-1325 3275);
|
|
DISPLAY 0.872340 (-1325 3275);
|
|
PAINT ORANGE (-1325 3275);
|
|
DISPLAY INVISIBLE (-1325 3275);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1325 3275);
|
|
DISPLAY 0.872340 (-1325 3275);
|
|
PAINT ORANGE (-1325 3275);
|
|
DISPLAY INVISIBLE (-1325 3275);
|
|
FORCEPROP 1 LAST PATH I37
|
|
J 0
|
|
(-1650 3450);
|
|
DISPLAY 0.872340 (-1650 3450);
|
|
PAINT PINK (-1650 3450);
|
|
DISPLAY INVISIBLE (-1650 3450);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1650 3400);
|
|
DISPLAY INVISIBLE (-1650 3400);
|
|
FORCEADD OUTPORT..1
|
|
(-1650 3475);
|
|
FORCEPROP 1 LASTPIN (-1700 3475) VHDL_PORT OUT
|
|
J 0
|
|
(-1685 3405);
|
|
DISPLAY 0.872340 (-1685 3405);
|
|
PAINT PINK (-1685 3405);
|
|
DISPLAY INVISIBLE (-1685 3405);
|
|
FORCEPROP 1 LASTPIN (-1700 3475) HDL_PORT OUT
|
|
J 0
|
|
(-1325 3350);
|
|
DISPLAY 0.872340 (-1325 3350);
|
|
PAINT ORANGE (-1325 3350);
|
|
DISPLAY INVISIBLE (-1325 3350);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1325 3350);
|
|
DISPLAY 0.872340 (-1325 3350);
|
|
PAINT ORANGE (-1325 3350);
|
|
DISPLAY INVISIBLE (-1325 3350);
|
|
FORCEPROP 1 LAST PATH I38
|
|
J 0
|
|
(-1650 3525);
|
|
DISPLAY 0.872340 (-1650 3525);
|
|
PAINT PINK (-1650 3525);
|
|
DISPLAY INVISIBLE (-1650 3525);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1650 3475);
|
|
DISPLAY INVISIBLE (-1650 3475);
|
|
FORCEADD INPORT..1
|
|
(925 3650);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1250 3525);
|
|
DISPLAY 0.872340 (1250 3525);
|
|
PAINT ORANGE (1250 3525);
|
|
DISPLAY INVISIBLE (1250 3525);
|
|
FORCEPROP 1 LASTPIN (975 3650) HDL_PORT IN
|
|
J 0
|
|
(1250 3525);
|
|
DISPLAY 0.872340 (1250 3525);
|
|
PAINT ORANGE (1250 3525);
|
|
DISPLAY INVISIBLE (1250 3525);
|
|
FORCEPROP 1 LASTPIN (975 3650) VHDL_PORT IN
|
|
J 0
|
|
(990 3580);
|
|
DISPLAY 0.872340 (990 3580);
|
|
PAINT PINK (990 3580);
|
|
DISPLAY INVISIBLE (990 3580);
|
|
FORCEPROP 1 LAST PATH I39
|
|
J 0
|
|
(900 3700);
|
|
DISPLAY 0.872340 (900 3700);
|
|
PAINT PINK (900 3700);
|
|
DISPLAY INVISIBLE (900 3700);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(925 3650);
|
|
DISPLAY INVISIBLE (925 3650);
|
|
FORCEADD GENERAL_UTILITIES..1
|
|
(-2700 2675);
|
|
FORCEPROP 2 LASTPIN (-3525 3450) SIG_NAME UN$1$GENERALUTILITIES$I4$GENERICPULSEIN
|
|
J 0
|
|
(-3515 3460);
|
|
DISPLAY 0.659574 (-3515 3460);
|
|
PAINT MONO (-3515 3460);
|
|
DISPLAY INVISIBLE (-3515 3460);
|
|
FORCEPROP 2 LASTPIN (-3525 3375) SIG_NAME UN$1$GENERALUTILITIES$I4$GENERICDELAYIN
|
|
J 0
|
|
(-3515 3385);
|
|
DISPLAY 0.659574 (-3515 3385);
|
|
PAINT MONO (-3515 3385);
|
|
DISPLAY INVISIBLE (-3515 3385);
|
|
FORCEPROP 2 LAST PATH I4
|
|
J 0
|
|
(-2100 3225);
|
|
DISPLAY 1.021277 (-2100 3225);
|
|
PAINT ORANGE (-2100 3225);
|
|
FORCEPROP 1 LASTPIN (-3525 3300) VHDL_MODE IN
|
|
J 2
|
|
(-3545 3233);
|
|
DISPLAY INVISIBLE (-3545 3233);
|
|
FORCEPROP 1 LASTPIN (-3525 2975) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2908);
|
|
DISPLAY INVISIBLE (-3545 2908);
|
|
FORCEPROP 1 LASTPIN (-3525 3175) VHDL_MODE IN
|
|
J 2
|
|
(-3545 3108);
|
|
DISPLAY INVISIBLE (-3545 3108);
|
|
FORCEPROP 1 LASTPIN (-3525 3225) VHDL_MODE IN
|
|
J 2
|
|
(-3545 3158);
|
|
DISPLAY INVISIBLE (-3545 3158);
|
|
FORCEPROP 1 LASTPIN (-3525 2900) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2833);
|
|
DISPLAY INVISIBLE (-3545 2833);
|
|
FORCEPROP 1 LASTPIN (-3525 2300) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2233);
|
|
DISPLAY INVISIBLE (-3545 2233);
|
|
FORCEPROP 1 LASTPIN (-3525 2375) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2308);
|
|
DISPLAY INVISIBLE (-3545 2308);
|
|
FORCEPROP 1 LASTPIN (-3525 2450) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2383);
|
|
DISPLAY INVISIBLE (-3545 2383);
|
|
FORCEPROP 1 LASTPIN (-3525 2525) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2458);
|
|
DISPLAY INVISIBLE (-3545 2458);
|
|
FORCEPROP 1 LASTPIN (-3525 2625) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2558);
|
|
DISPLAY INVISIBLE (-3545 2558);
|
|
FORCEPROP 1 LASTPIN (-3525 2675) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2608);
|
|
DISPLAY INVISIBLE (-3545 2608);
|
|
FORCEPROP 1 LASTPIN (-3525 2750) VHDL_MODE IN
|
|
J 2
|
|
(-3545 2683);
|
|
DISPLAY INVISIBLE (-3545 2683);
|
|
FORCEPROP 1 LASTPIN (-2150 2275) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2208);
|
|
DISPLAY INVISIBLE (-2130 2208);
|
|
FORCEPROP 1 LASTPIN (-2150 2350) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2283);
|
|
DISPLAY INVISIBLE (-2130 2283);
|
|
FORCEPROP 1 LASTPIN (-2150 2425) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2358);
|
|
DISPLAY INVISIBLE (-2130 2358);
|
|
FORCEPROP 1 LASTPIN (-2150 2500) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2433);
|
|
DISPLAY INVISIBLE (-2130 2433);
|
|
FORCEPROP 1 LASTPIN (-2150 2600) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2533);
|
|
DISPLAY INVISIBLE (-2130 2533);
|
|
FORCEPROP 1 LASTPIN (-2150 2775) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2708);
|
|
DISPLAY INVISIBLE (-2130 2708);
|
|
FORCEPROP 1 LASTPIN (-2150 2950) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 2883);
|
|
DISPLAY INVISIBLE (-2130 2883);
|
|
FORCEPROP 1 LASTPIN (-2150 3125) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 3058);
|
|
DISPLAY INVISIBLE (-2130 3058);
|
|
FORCEPROP 1 LASTPIN (-2150 3225) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 3158);
|
|
DISPLAY INVISIBLE (-2130 3158);
|
|
FORCEPROP 1 LASTPIN (-2150 3325) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 3258);
|
|
DISPLAY INVISIBLE (-2130 3258);
|
|
FORCEPROP 1 LASTPIN (-2150 3400) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 3333);
|
|
DISPLAY INVISIBLE (-2130 3333);
|
|
FORCEPROP 1 LASTPIN (-2150 3475) VHDL_MODE OUT
|
|
J 0
|
|
(-2130 3408);
|
|
DISPLAY INVISIBLE (-2130 3408);
|
|
FORCEPROP 1 LASTPIN (-3525 3375) VHDL_MODE IN
|
|
J 2
|
|
(-3545 3308);
|
|
DISPLAY INVISIBLE (-3545 3308);
|
|
FORCEPROP 1 LASTPIN (-3525 3450) VHDL_MODE IN
|
|
J 2
|
|
(-3545 3383);
|
|
DISPLAY INVISIBLE (-3545 3383);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-2700 2675);
|
|
DISPLAY INVISIBLE (-2700 2675);
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|
FORCEPROP 1 LAST BLOCK TRUE
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|
J 1
|
|
(-2700 2685);
|
|
DISPLAY INVISIBLE (-2700 2685);
|
|
FORCEPROP 1 LASTPIN (-3525 2850) VHDL_MODE IN
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J 2
|
|
(-3545 2783);
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|
DISPLAY INVISIBLE (-3545 2783);
|
|
FORCEADD INPORT..1
|
|
(925 3600);
|
|
FORCEPROP 1 LASTPIN (975 3600) VHDL_PORT IN
|
|
J 0
|
|
(990 3530);
|
|
DISPLAY 0.872340 (990 3530);
|
|
PAINT PINK (990 3530);
|
|
DISPLAY INVISIBLE (990 3530);
|
|
FORCEPROP 1 LASTPIN (975 3600) HDL_PORT IN
|
|
J 0
|
|
(1250 3475);
|
|
DISPLAY 0.872340 (1250 3475);
|
|
PAINT ORANGE (1250 3475);
|
|
DISPLAY INVISIBLE (1250 3475);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1250 3475);
|
|
DISPLAY 0.872340 (1250 3475);
|
|
PAINT ORANGE (1250 3475);
|
|
DISPLAY INVISIBLE (1250 3475);
|
|
FORCEPROP 1 LAST PATH I40
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|
J 0
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|
(900 3650);
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|
DISPLAY 0.872340 (900 3650);
|
|
PAINT PINK (900 3650);
|
|
DISPLAY INVISIBLE (900 3650);
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|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(925 3600);
|
|
DISPLAY INVISIBLE (925 3600);
|
|
FORCEADD INPORT..1
|
|
(925 3475);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
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J 0
|
|
(1250 3350);
|
|
DISPLAY 0.872340 (1250 3350);
|
|
PAINT ORANGE (1250 3350);
|
|
DISPLAY INVISIBLE (1250 3350);
|
|
FORCEPROP 1 LASTPIN (975 3475) HDL_PORT IN
|
|
J 0
|
|
(1250 3350);
|
|
DISPLAY 0.872340 (1250 3350);
|
|
PAINT ORANGE (1250 3350);
|
|
DISPLAY INVISIBLE (1250 3350);
|
|
FORCEPROP 1 LASTPIN (975 3475) VHDL_PORT IN
|
|
J 0
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|
(990 3405);
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|
DISPLAY 0.872340 (990 3405);
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|
PAINT PINK (990 3405);
|
|
DISPLAY INVISIBLE (990 3405);
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FORCEPROP 1 LAST PATH I41
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J 0
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|
(900 3525);
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|
DISPLAY 0.872340 (900 3525);
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|
PAINT PINK (900 3525);
|
|
DISPLAY INVISIBLE (900 3525);
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|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(925 3475);
|
|
DISPLAY INVISIBLE (925 3475);
|
|
FORCEADD INPORT..1
|
|
(925 3425);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
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|
J 0
|
|
(1250 3300);
|
|
DISPLAY 0.872340 (1250 3300);
|
|
PAINT ORANGE (1250 3300);
|
|
DISPLAY INVISIBLE (1250 3300);
|
|
FORCEPROP 1 LASTPIN (975 3425) HDL_PORT IN
|
|
J 0
|
|
(1250 3300);
|
|
DISPLAY 0.872340 (1250 3300);
|
|
PAINT ORANGE (1250 3300);
|
|
DISPLAY INVISIBLE (1250 3300);
|
|
FORCEPROP 1 LASTPIN (975 3425) VHDL_PORT IN
|
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J 0
|
|
(990 3355);
|
|
DISPLAY 0.872340 (990 3355);
|
|
PAINT PINK (990 3355);
|
|
DISPLAY INVISIBLE (990 3355);
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FORCEPROP 1 LAST PATH I42
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J 0
|
|
(900 3475);
|
|
DISPLAY 0.872340 (900 3475);
|
|
PAINT PINK (900 3475);
|
|
DISPLAY INVISIBLE (900 3475);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(925 3425);
|
|
DISPLAY INVISIBLE (925 3425);
|
|
FORCEADD INPORT..1
|
|
(950 3275);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1275 3150);
|
|
DISPLAY 0.872340 (1275 3150);
|
|
PAINT ORANGE (1275 3150);
|
|
DISPLAY INVISIBLE (1275 3150);
|
|
FORCEPROP 1 LASTPIN (1000 3275) HDL_PORT IN
|
|
J 0
|
|
(1275 3150);
|
|
DISPLAY 0.872340 (1275 3150);
|
|
PAINT ORANGE (1275 3150);
|
|
DISPLAY INVISIBLE (1275 3150);
|
|
FORCEPROP 1 LASTPIN (1000 3275) VHDL_PORT IN
|
|
J 0
|
|
(1015 3205);
|
|
DISPLAY 0.872340 (1015 3205);
|
|
PAINT PINK (1015 3205);
|
|
DISPLAY INVISIBLE (1015 3205);
|
|
FORCEPROP 1 LAST PATH I43
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J 0
|
|
(925 3325);
|
|
DISPLAY 0.872340 (925 3325);
|
|
PAINT PINK (925 3325);
|
|
DISPLAY INVISIBLE (925 3325);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(950 3275);
|
|
DISPLAY INVISIBLE (950 3275);
|
|
FORCEADD INPORT..1
|
|
(950 3200);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1275 3075);
|
|
DISPLAY 0.872340 (1275 3075);
|
|
PAINT ORANGE (1275 3075);
|
|
DISPLAY INVISIBLE (1275 3075);
|
|
FORCEPROP 1 LASTPIN (1000 3200) HDL_PORT IN
|
|
J 0
|
|
(1275 3075);
|
|
DISPLAY 0.872340 (1275 3075);
|
|
PAINT ORANGE (1275 3075);
|
|
DISPLAY INVISIBLE (1275 3075);
|
|
FORCEPROP 1 LASTPIN (1000 3200) VHDL_PORT IN
|
|
J 0
|
|
(1015 3130);
|
|
DISPLAY 0.872340 (1015 3130);
|
|
PAINT PINK (1015 3130);
|
|
DISPLAY INVISIBLE (1015 3130);
|
|
FORCEPROP 1 LAST PATH I44
|
|
J 0
|
|
(925 3250);
|
|
DISPLAY 0.872340 (925 3250);
|
|
PAINT PINK (925 3250);
|
|
DISPLAY INVISIBLE (925 3250);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(950 3200);
|
|
DISPLAY INVISIBLE (950 3200);
|
|
FORCEADD INPORT..1
|
|
(900 3125);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(900 3125);
|
|
DISPLAY INVISIBLE (900 3125);
|
|
FORCEPROP 1 LAST PATH I45
|
|
J 0
|
|
(875 3175);
|
|
DISPLAY 0.872340 (875 3175);
|
|
PAINT PINK (875 3175);
|
|
DISPLAY INVISIBLE (875 3175);
|
|
FORCEPROP 1 LASTPIN (950 3125) VHDL_PORT IN
|
|
J 0
|
|
(965 3055);
|
|
DISPLAY 0.872340 (965 3055);
|
|
PAINT PINK (965 3055);
|
|
DISPLAY INVISIBLE (965 3055);
|
|
FORCEPROP 1 LASTPIN (950 3125) HDL_PORT IN
|
|
J 0
|
|
(1225 3000);
|
|
DISPLAY 0.872340 (1225 3000);
|
|
PAINT ORANGE (1225 3000);
|
|
DISPLAY INVISIBLE (1225 3000);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1225 3000);
|
|
DISPLAY 0.872340 (1225 3000);
|
|
PAINT ORANGE (1225 3000);
|
|
DISPLAY INVISIBLE (1225 3000);
|
|
FORCEADD OUTPORT..1
|
|
(3200 2925);
|
|
FORCEPROP 1 LASTPIN (3150 2925) VHDL_PORT OUT
|
|
J 0
|
|
(3165 2855);
|
|
DISPLAY 0.872340 (3165 2855);
|
|
PAINT PINK (3165 2855);
|
|
DISPLAY INVISIBLE (3165 2855);
|
|
FORCEPROP 1 LASTPIN (3150 2925) HDL_PORT OUT
|
|
J 0
|
|
(3525 2800);
|
|
DISPLAY 0.872340 (3525 2800);
|
|
PAINT ORANGE (3525 2800);
|
|
DISPLAY INVISIBLE (3525 2800);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3525 2800);
|
|
DISPLAY 0.872340 (3525 2800);
|
|
PAINT ORANGE (3525 2800);
|
|
DISPLAY INVISIBLE (3525 2800);
|
|
FORCEPROP 1 LAST PATH I46
|
|
J 0
|
|
(3200 2975);
|
|
DISPLAY 0.872340 (3200 2975);
|
|
PAINT PINK (3200 2975);
|
|
DISPLAY INVISIBLE (3200 2975);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3200 2925);
|
|
DISPLAY INVISIBLE (3200 2925);
|
|
FORCEADD OUTPORT..1
|
|
(3200 2975);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3525 2850);
|
|
DISPLAY 0.872340 (3525 2850);
|
|
PAINT ORANGE (3525 2850);
|
|
DISPLAY INVISIBLE (3525 2850);
|
|
FORCEPROP 1 LASTPIN (3150 2975) HDL_PORT OUT
|
|
J 0
|
|
(3525 2850);
|
|
DISPLAY 0.872340 (3525 2850);
|
|
PAINT ORANGE (3525 2850);
|
|
DISPLAY INVISIBLE (3525 2850);
|
|
FORCEPROP 1 LASTPIN (3150 2975) VHDL_PORT OUT
|
|
J 0
|
|
(3165 2905);
|
|
DISPLAY 0.872340 (3165 2905);
|
|
PAINT PINK (3165 2905);
|
|
DISPLAY INVISIBLE (3165 2905);
|
|
FORCEPROP 1 LAST PATH I47
|
|
J 0
|
|
(3200 3025);
|
|
DISPLAY 0.872340 (3200 3025);
|
|
PAINT PINK (3200 3025);
|
|
DISPLAY INVISIBLE (3200 3025);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3200 2975);
|
|
DISPLAY INVISIBLE (3200 2975);
|
|
FORCEADD OUTPORT..1
|
|
(3150 3275);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3150 3275);
|
|
DISPLAY INVISIBLE (3150 3275);
|
|
FORCEPROP 1 LAST PATH I48
|
|
J 0
|
|
(3150 3325);
|
|
DISPLAY 0.872340 (3150 3325);
|
|
PAINT PINK (3150 3325);
|
|
DISPLAY INVISIBLE (3150 3325);
|
|
FORCEPROP 1 LASTPIN (3100 3275) HDL_PORT OUT
|
|
J 0
|
|
(3475 3150);
|
|
DISPLAY 0.872340 (3475 3150);
|
|
PAINT ORANGE (3475 3150);
|
|
DISPLAY INVISIBLE (3475 3150);
|
|
FORCEPROP 1 LASTPIN (3100 3275) VHDL_PORT OUT
|
|
J 0
|
|
(3115 3205);
|
|
DISPLAY 0.872340 (3115 3205);
|
|
PAINT PINK (3115 3205);
|
|
DISPLAY INVISIBLE (3115 3205);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3475 3150);
|
|
DISPLAY 0.872340 (3475 3150);
|
|
PAINT ORANGE (3475 3150);
|
|
DISPLAY INVISIBLE (3475 3150);
|
|
FORCEADD OUTPORT..1
|
|
(3150 3375);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3475 3250);
|
|
DISPLAY 0.872340 (3475 3250);
|
|
PAINT ORANGE (3475 3250);
|
|
DISPLAY INVISIBLE (3475 3250);
|
|
FORCEPROP 1 LASTPIN (3100 3375) HDL_PORT OUT
|
|
J 0
|
|
(3475 3250);
|
|
DISPLAY 0.872340 (3475 3250);
|
|
PAINT ORANGE (3475 3250);
|
|
DISPLAY INVISIBLE (3475 3250);
|
|
FORCEPROP 1 LASTPIN (3100 3375) VHDL_PORT OUT
|
|
J 0
|
|
(3115 3305);
|
|
DISPLAY 0.872340 (3115 3305);
|
|
PAINT PINK (3115 3305);
|
|
DISPLAY INVISIBLE (3115 3305);
|
|
FORCEPROP 1 LAST PATH I49
|
|
J 0
|
|
(3150 3425);
|
|
DISPLAY 0.872340 (3150 3425);
|
|
PAINT PINK (3150 3425);
|
|
DISPLAY INVISIBLE (3150 3425);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3150 3375);
|
|
DISPLAY INVISIBLE (3150 3375);
|
|
FORCEADD POWER..1
|
|
(3225 925);
|
|
FORCEPROP 2 LAST PATH I5
|
|
J 0
|
|
(3525 1375);
|
|
DISPLAY 1.021277 (3525 1375);
|
|
PAINT ORANGE (3525 1375);
|
|
FORCEPROP 1 LASTPIN (2725 1100) VHDL_MODE IN
|
|
J 2
|
|
(2705 1033);
|
|
DISPLAY INVISIBLE (2705 1033);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(3225 935);
|
|
DISPLAY INVISIBLE (3225 935);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(3225 925);
|
|
DISPLAY INVISIBLE (3225 925);
|
|
FORCEADD OUTPORT..1
|
|
(3150 3425);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3475 3300);
|
|
DISPLAY 0.872340 (3475 3300);
|
|
PAINT ORANGE (3475 3300);
|
|
DISPLAY INVISIBLE (3475 3300);
|
|
FORCEPROP 1 LASTPIN (3100 3425) HDL_PORT OUT
|
|
J 0
|
|
(3475 3300);
|
|
DISPLAY 0.872340 (3475 3300);
|
|
PAINT ORANGE (3475 3300);
|
|
DISPLAY INVISIBLE (3475 3300);
|
|
FORCEPROP 1 LASTPIN (3100 3425) VHDL_PORT OUT
|
|
J 0
|
|
(3115 3355);
|
|
DISPLAY 0.872340 (3115 3355);
|
|
PAINT PINK (3115 3355);
|
|
DISPLAY INVISIBLE (3115 3355);
|
|
FORCEPROP 1 LAST PATH I50
|
|
J 0
|
|
(3150 3475);
|
|
DISPLAY 0.872340 (3150 3475);
|
|
PAINT PINK (3150 3475);
|
|
DISPLAY INVISIBLE (3150 3475);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3150 3425);
|
|
DISPLAY INVISIBLE (3150 3425);
|
|
FORCEADD OUTPORT..1
|
|
(3125 3525);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3450 3400);
|
|
DISPLAY 0.872340 (3450 3400);
|
|
PAINT ORANGE (3450 3400);
|
|
DISPLAY INVISIBLE (3450 3400);
|
|
FORCEPROP 1 LASTPIN (3075 3525) HDL_PORT OUT
|
|
J 0
|
|
(3450 3400);
|
|
DISPLAY 0.872340 (3450 3400);
|
|
PAINT ORANGE (3450 3400);
|
|
DISPLAY INVISIBLE (3450 3400);
|
|
FORCEPROP 1 LASTPIN (3075 3525) VHDL_PORT OUT
|
|
J 0
|
|
(3090 3455);
|
|
DISPLAY 0.872340 (3090 3455);
|
|
PAINT PINK (3090 3455);
|
|
DISPLAY INVISIBLE (3090 3455);
|
|
FORCEPROP 1 LAST PATH I51
|
|
J 0
|
|
(3125 3575);
|
|
DISPLAY 0.872340 (3125 3575);
|
|
PAINT PINK (3125 3575);
|
|
DISPLAY INVISIBLE (3125 3575);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3125 3525);
|
|
DISPLAY INVISIBLE (3125 3525);
|
|
FORCEADD OUTPORT..1
|
|
(3125 3600);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3450 3475);
|
|
DISPLAY 0.872340 (3450 3475);
|
|
PAINT ORANGE (3450 3475);
|
|
DISPLAY INVISIBLE (3450 3475);
|
|
FORCEPROP 1 LASTPIN (3075 3600) HDL_PORT OUT
|
|
J 0
|
|
(3450 3475);
|
|
DISPLAY 0.872340 (3450 3475);
|
|
PAINT ORANGE (3450 3475);
|
|
DISPLAY INVISIBLE (3450 3475);
|
|
FORCEPROP 1 LASTPIN (3075 3600) VHDL_PORT OUT
|
|
J 0
|
|
(3090 3530);
|
|
DISPLAY 0.872340 (3090 3530);
|
|
PAINT PINK (3090 3530);
|
|
DISPLAY INVISIBLE (3090 3530);
|
|
FORCEPROP 1 LAST PATH I52
|
|
J 0
|
|
(3125 3650);
|
|
DISPLAY 0.872340 (3125 3650);
|
|
PAINT PINK (3125 3650);
|
|
DISPLAY INVISIBLE (3125 3650);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3125 3600);
|
|
DISPLAY INVISIBLE (3125 3600);
|
|
FORCEADD HCT238..1
|
|
(450 2625);
|
|
FORCEPROP 2 LAST $LOCATION U61
|
|
J 0
|
|
(475 2950);
|
|
DISPLAY 0.680851 (475 2950);
|
|
PAINT MONO (475 2950);
|
|
FORCEPROP 2 LAST CDS_LOCATION U61
|
|
J 0
|
|
(475 3000);
|
|
DISPLAY 1.021277 (475 3000);
|
|
PAINT ORANGE (475 3000);
|
|
DISPLAY INVISIBLE (475 3000);
|
|
FORCEPROP 2 LAST $SEC 1
|
|
J 0
|
|
(475 3000);
|
|
DISPLAY 0.680851 (475 3000);
|
|
PAINT MONO (475 3000);
|
|
DISPLAY INVISIBLE (475 3000);
|
|
FORCEPROP 2 LAST CDS_SEC 1
|
|
J 0
|
|
(475 3000);
|
|
DISPLAY 1.021277 (475 3000);
|
|
PAINT ORANGE (475 3000);
|
|
DISPLAY INVISIBLE (475 3000);
|
|
FORCEPROP 2 LASTPIN (275 2800) $PN 1
|
|
J 2
|
|
(265 2810);
|
|
DISPLAY 0.808511 (265 2810);
|
|
PAINT ORANGE (265 2810);
|
|
FORCEPROP 2 LASTPIN (275 2700) $PN 2
|
|
J 2
|
|
(265 2710);
|
|
DISPLAY 0.808511 (265 2710);
|
|
PAINT ORANGE (265 2710);
|
|
FORCEPROP 2 LASTPIN (275 2600) $PN 3
|
|
J 2
|
|
(265 2610);
|
|
DISPLAY 0.808511 (265 2610);
|
|
PAINT ORANGE (265 2610);
|
|
FORCEPROP 2 LASTPIN (350 2375) $PN 4
|
|
R 1
|
|
J 2
|
|
(340 2365);
|
|
DISPLAY 0.808511 (340 2365);
|
|
PAINT ORANGE (340 2365);
|
|
FORCEPROP 2 LASTPIN (450 2375) $PN 5
|
|
R 1
|
|
J 2
|
|
(440 2365);
|
|
DISPLAY 0.808511 (440 2365);
|
|
PAINT ORANGE (440 2365);
|
|
FORCEPROP 2 LASTPIN (525 2375) $PN 6
|
|
R 1
|
|
J 2
|
|
(515 2365);
|
|
DISPLAY 0.808511 (515 2365);
|
|
PAINT ORANGE (515 2365);
|
|
FORCEPROP 2 LASTPIN (625 2800) $PN 15
|
|
J 0
|
|
(635 2810);
|
|
DISPLAY 0.808511 (635 2810);
|
|
PAINT ORANGE (635 2810);
|
|
FORCEPROP 2 LASTPIN (625 2750) $PN 14
|
|
J 0
|
|
(635 2760);
|
|
DISPLAY 0.808511 (635 2760);
|
|
PAINT ORANGE (635 2760);
|
|
FORCEPROP 2 LASTPIN (625 2700) $PN 13
|
|
J 0
|
|
(635 2710);
|
|
DISPLAY 0.808511 (635 2710);
|
|
PAINT ORANGE (635 2710);
|
|
FORCEPROP 2 LASTPIN (625 2650) $PN 12
|
|
J 0
|
|
(635 2660);
|
|
DISPLAY 0.808511 (635 2660);
|
|
PAINT ORANGE (635 2660);
|
|
FORCEPROP 2 LASTPIN (625 2600) $PN 11
|
|
J 0
|
|
(635 2610);
|
|
DISPLAY 0.808511 (635 2610);
|
|
PAINT ORANGE (635 2610);
|
|
FORCEPROP 2 LASTPIN (625 2550) $PN 10
|
|
J 0
|
|
(635 2560);
|
|
DISPLAY 0.808511 (635 2560);
|
|
PAINT ORANGE (635 2560);
|
|
FORCEPROP 2 LASTPIN (625 2500) $PN 9
|
|
J 0
|
|
(635 2510);
|
|
DISPLAY 0.808511 (635 2510);
|
|
PAINT ORANGE (635 2510);
|
|
FORCEPROP 2 LASTPIN (625 2450) $PN 7
|
|
J 0
|
|
(635 2460);
|
|
DISPLAY 0.808511 (635 2460);
|
|
PAINT ORANGE (635 2460);
|
|
FORCEPROP 2 LAST PACK_TYPE TSSOP
|
|
J 0
|
|
(475 2900);
|
|
DISPLAY 1.021277 (475 2900);
|
|
PAINT ORANGE (475 2900);
|
|
FORCEPROP 2 LAST PATH I53
|
|
J 0
|
|
(475 2850);
|
|
DISPLAY 1.021277 (475 2850);
|
|
PAINT ORANGE (475 2850);
|
|
FORCEPROP 1 LAST CDS_LMAN_SYM_OUTLINE -125,200,125,-200
|
|
J 0
|
|
(450 2625);
|
|
DISPLAY 0.468085 (450 2625);
|
|
PAINT GREEN (450 2625);
|
|
DISPLAY INVISIBLE (450 2625);
|
|
FORCEPROP 2 LAST CDS_LIB ttl
|
|
J 0
|
|
(450 2625);
|
|
DISPLAY INVISIBLE (450 2625);
|
|
FORCEPROP 2 LASTPIN (275 2800) SIG_NAME UN$1$HCT238$I53$A0
|
|
J 0
|
|
(285 2810);
|
|
DISPLAY 0.659574 (285 2810);
|
|
PAINT MONO (285 2810);
|
|
DISPLAY INVISIBLE (285 2810);
|
|
FORCEPROP 2 LASTPIN (275 2700) SIG_NAME UN$1$HCT238$I53$A1
|
|
J 0
|
|
(285 2710);
|
|
DISPLAY 0.659574 (285 2710);
|
|
PAINT MONO (285 2710);
|
|
DISPLAY INVISIBLE (285 2710);
|
|
FORCEPROP 2 LASTPIN (275 2600) SIG_NAME UN$1$HCT238$I53$A2
|
|
J 0
|
|
(285 2610);
|
|
DISPLAY 0.659574 (285 2610);
|
|
PAINT MONO (285 2610);
|
|
DISPLAY INVISIBLE (285 2610);
|
|
FORCEPROP 2 LASTPIN (525 2375) SIG_NAME UN$1$HCT238$I53$E3
|
|
J 0
|
|
(535 2385);
|
|
DISPLAY 0.659574 (535 2385);
|
|
PAINT MONO (535 2385);
|
|
DISPLAY INVISIBLE (535 2385);
|
|
FORCEADD INPORT..1
|
|
(950 1875);
|
|
FORCEPROP 1 LASTPIN (1000 1875) VHDL_PORT IN
|
|
J 0
|
|
(1015 1805);
|
|
DISPLAY 0.872340 (1015 1805);
|
|
PAINT PINK (1015 1805);
|
|
DISPLAY INVISIBLE (1015 1805);
|
|
FORCEPROP 1 LASTPIN (1000 1875) HDL_PORT IN
|
|
J 0
|
|
(1275 1750);
|
|
DISPLAY 0.872340 (1275 1750);
|
|
PAINT ORANGE (1275 1750);
|
|
DISPLAY INVISIBLE (1275 1750);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(1275 1750);
|
|
DISPLAY 0.872340 (1275 1750);
|
|
PAINT ORANGE (1275 1750);
|
|
DISPLAY INVISIBLE (1275 1750);
|
|
FORCEPROP 1 LAST PATH I54
|
|
J 0
|
|
(925 1925);
|
|
DISPLAY 0.872340 (925 1925);
|
|
PAINT PINK (925 1925);
|
|
DISPLAY INVISIBLE (925 1925);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(950 1875);
|
|
DISPLAY INVISIBLE (950 1875);
|
|
FORCEADD OUTPORT..1
|
|
(2875 2375);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(2875 2375);
|
|
DISPLAY INVISIBLE (2875 2375);
|
|
FORCEPROP 1 LAST PATH I55
|
|
J 0
|
|
(2875 2425);
|
|
DISPLAY 0.872340 (2875 2425);
|
|
PAINT PINK (2875 2425);
|
|
DISPLAY INVISIBLE (2875 2425);
|
|
FORCEPROP 1 LASTPIN (2825 2375) VHDL_PORT OUT
|
|
J 0
|
|
(2840 2305);
|
|
DISPLAY 0.872340 (2840 2305);
|
|
PAINT PINK (2840 2305);
|
|
DISPLAY INVISIBLE (2840 2305);
|
|
FORCEPROP 1 LASTPIN (2825 2375) HDL_PORT OUT
|
|
J 0
|
|
(3200 2250);
|
|
DISPLAY 0.872340 (3200 2250);
|
|
PAINT ORANGE (3200 2250);
|
|
DISPLAY INVISIBLE (3200 2250);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3200 2250);
|
|
DISPLAY 0.872340 (3200 2250);
|
|
PAINT ORANGE (3200 2250);
|
|
DISPLAY INVISIBLE (3200 2250);
|
|
FORCEADD OUTPORT..1
|
|
(2875 2300);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(2875 2300);
|
|
DISPLAY INVISIBLE (2875 2300);
|
|
FORCEPROP 1 LAST PATH I56
|
|
J 0
|
|
(2875 2350);
|
|
DISPLAY 0.872340 (2875 2350);
|
|
PAINT PINK (2875 2350);
|
|
DISPLAY INVISIBLE (2875 2350);
|
|
FORCEPROP 1 LASTPIN (2825 2300) VHDL_PORT OUT
|
|
J 0
|
|
(2840 2230);
|
|
DISPLAY 0.872340 (2840 2230);
|
|
PAINT PINK (2840 2230);
|
|
DISPLAY INVISIBLE (2840 2230);
|
|
FORCEPROP 1 LASTPIN (2825 2300) HDL_PORT OUT
|
|
J 0
|
|
(3200 2175);
|
|
DISPLAY 0.872340 (3200 2175);
|
|
PAINT ORANGE (3200 2175);
|
|
DISPLAY INVISIBLE (3200 2175);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3200 2175);
|
|
DISPLAY 0.872340 (3200 2175);
|
|
PAINT ORANGE (3200 2175);
|
|
DISPLAY INVISIBLE (3200 2175);
|
|
FORCEADD OUTPORT..1
|
|
(2875 2200);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(2875 2200);
|
|
DISPLAY INVISIBLE (2875 2200);
|
|
FORCEPROP 1 LAST PATH I57
|
|
J 0
|
|
(2875 2250);
|
|
DISPLAY 0.872340 (2875 2250);
|
|
PAINT PINK (2875 2250);
|
|
DISPLAY INVISIBLE (2875 2250);
|
|
FORCEPROP 1 LASTPIN (2825 2200) VHDL_PORT OUT
|
|
J 0
|
|
(2840 2130);
|
|
DISPLAY 0.872340 (2840 2130);
|
|
PAINT PINK (2840 2130);
|
|
DISPLAY INVISIBLE (2840 2130);
|
|
FORCEPROP 1 LASTPIN (2825 2200) HDL_PORT OUT
|
|
J 0
|
|
(3200 2075);
|
|
DISPLAY 0.872340 (3200 2075);
|
|
PAINT ORANGE (3200 2075);
|
|
DISPLAY INVISIBLE (3200 2075);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3200 2075);
|
|
DISPLAY 0.872340 (3200 2075);
|
|
PAINT ORANGE (3200 2075);
|
|
DISPLAY INVISIBLE (3200 2075);
|
|
FORCEADD OUTPORT..1
|
|
(2875 2075);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(2875 2075);
|
|
DISPLAY INVISIBLE (2875 2075);
|
|
FORCEPROP 1 LAST PATH I58
|
|
J 0
|
|
(2875 2125);
|
|
DISPLAY 0.872340 (2875 2125);
|
|
PAINT PINK (2875 2125);
|
|
DISPLAY INVISIBLE (2875 2125);
|
|
FORCEPROP 1 LASTPIN (2825 2075) VHDL_PORT OUT
|
|
J 0
|
|
(2840 2005);
|
|
DISPLAY 0.872340 (2840 2005);
|
|
PAINT PINK (2840 2005);
|
|
DISPLAY INVISIBLE (2840 2005);
|
|
FORCEPROP 1 LASTPIN (2825 2075) HDL_PORT OUT
|
|
J 0
|
|
(3200 1950);
|
|
DISPLAY 0.872340 (3200 1950);
|
|
PAINT ORANGE (3200 1950);
|
|
DISPLAY INVISIBLE (3200 1950);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3200 1950);
|
|
DISPLAY 0.872340 (3200 1950);
|
|
PAINT ORANGE (3200 1950);
|
|
DISPLAY INVISIBLE (3200 1950);
|
|
FORCEADD OUTPORT..1
|
|
(2425 1200);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(2425 1200);
|
|
DISPLAY INVISIBLE (2425 1200);
|
|
FORCEPROP 1 LAST PATH I59
|
|
J 0
|
|
(2425 1250);
|
|
DISPLAY 0.872340 (2425 1250);
|
|
PAINT PINK (2425 1250);
|
|
DISPLAY INVISIBLE (2425 1250);
|
|
FORCEPROP 1 LASTPIN (2375 1200) VHDL_PORT OUT
|
|
J 0
|
|
(2390 1130);
|
|
DISPLAY 0.872340 (2390 1130);
|
|
PAINT PINK (2390 1130);
|
|
DISPLAY INVISIBLE (2390 1130);
|
|
FORCEPROP 1 LASTPIN (2375 1200) HDL_PORT OUT
|
|
J 0
|
|
(2750 1075);
|
|
DISPLAY 0.872340 (2750 1075);
|
|
PAINT ORANGE (2750 1075);
|
|
DISPLAY INVISIBLE (2750 1075);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(2750 1075);
|
|
DISPLAY 0.872340 (2750 1075);
|
|
PAINT ORANGE (2750 1075);
|
|
DISPLAY INVISIBLE (2750 1075);
|
|
FORCEADD ECAL_CONTROL..1
|
|
(1400 1150);
|
|
FORCEPROP 2 LAST PATH I6
|
|
J 0
|
|
(1700 1650);
|
|
DISPLAY 1.021277 (1700 1650);
|
|
PAINT ORANGE (1700 1650);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(1400 1150);
|
|
DISPLAY INVISIBLE (1400 1150);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(1400 1160);
|
|
DISPLAY INVISIBLE (1400 1160);
|
|
FORCEPROP 1 LASTPIN (950 1300) VHDL_MODE IN
|
|
J 2
|
|
(930 1233);
|
|
DISPLAY INVISIBLE (930 1233);
|
|
FORCEPROP 1 LASTPIN (950 1175) VHDL_MODE IN
|
|
J 2
|
|
(930 1108);
|
|
DISPLAY INVISIBLE (930 1108);
|
|
FORCEPROP 1 LASTPIN (950 1050) VHDL_MODE IN
|
|
J 2
|
|
(930 983);
|
|
DISPLAY INVISIBLE (930 983);
|
|
FORCEPROP 1 LASTPIN (1850 1200) VHDL_MODE OUT
|
|
J 0
|
|
(1870 1133);
|
|
DISPLAY INVISIBLE (1870 1133);
|
|
FORCEADD INPORT..1
|
|
(350 1050);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(350 1050);
|
|
DISPLAY INVISIBLE (350 1050);
|
|
FORCEPROP 1 LAST PATH I60
|
|
J 0
|
|
(325 1100);
|
|
DISPLAY 0.872340 (325 1100);
|
|
PAINT PINK (325 1100);
|
|
DISPLAY INVISIBLE (325 1100);
|
|
FORCEPROP 1 LASTPIN (400 1050) VHDL_PORT IN
|
|
J 0
|
|
(415 980);
|
|
DISPLAY 0.872340 (415 980);
|
|
PAINT PINK (415 980);
|
|
DISPLAY INVISIBLE (415 980);
|
|
FORCEPROP 1 LASTPIN (400 1050) HDL_PORT IN
|
|
J 0
|
|
(675 925);
|
|
DISPLAY 0.872340 (675 925);
|
|
PAINT ORANGE (675 925);
|
|
DISPLAY INVISIBLE (675 925);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(675 925);
|
|
DISPLAY 0.872340 (675 925);
|
|
PAINT ORANGE (675 925);
|
|
DISPLAY INVISIBLE (675 925);
|
|
FORCEADD OUTPORT..1
|
|
(375 450);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(375 450);
|
|
DISPLAY INVISIBLE (375 450);
|
|
FORCEPROP 1 LAST PATH I61
|
|
J 0
|
|
(375 500);
|
|
DISPLAY 0.872340 (375 500);
|
|
PAINT PINK (375 500);
|
|
DISPLAY INVISIBLE (375 500);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(700 325);
|
|
DISPLAY 0.872340 (700 325);
|
|
PAINT ORANGE (700 325);
|
|
DISPLAY INVISIBLE (700 325);
|
|
FORCEPROP 1 LASTPIN (325 450) HDL_PORT OUT
|
|
J 0
|
|
(700 325);
|
|
DISPLAY 0.872340 (700 325);
|
|
PAINT ORANGE (700 325);
|
|
DISPLAY INVISIBLE (700 325);
|
|
FORCEPROP 1 LASTPIN (325 450) VHDL_PORT OUT
|
|
J 0
|
|
(340 380);
|
|
DISPLAY 0.872340 (340 380);
|
|
PAINT PINK (340 380);
|
|
DISPLAY INVISIBLE (340 380);
|
|
FORCEADD OUTPORT..1
|
|
(375 350);
|
|
FORCEPROP 1 LASTPIN (325 350) VHDL_PORT OUT
|
|
J 0
|
|
(340 280);
|
|
DISPLAY 0.872340 (340 280);
|
|
PAINT PINK (340 280);
|
|
DISPLAY INVISIBLE (340 280);
|
|
FORCEPROP 1 LASTPIN (325 350) HDL_PORT OUT
|
|
J 0
|
|
(700 225);
|
|
DISPLAY 0.872340 (700 225);
|
|
PAINT ORANGE (700 225);
|
|
DISPLAY INVISIBLE (700 225);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(700 225);
|
|
DISPLAY 0.872340 (700 225);
|
|
PAINT ORANGE (700 225);
|
|
DISPLAY INVISIBLE (700 225);
|
|
FORCEPROP 1 LAST PATH I62
|
|
J 0
|
|
(375 400);
|
|
DISPLAY 0.872340 (375 400);
|
|
PAINT PINK (375 400);
|
|
DISPLAY INVISIBLE (375 400);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(375 350);
|
|
DISPLAY INVISIBLE (375 350);
|
|
FORCEADD OUTPORT..1
|
|
(375 700);
|
|
FORCEPROP 1 LASTPIN (325 700) VHDL_PORT OUT
|
|
J 0
|
|
(340 630);
|
|
DISPLAY 0.872340 (340 630);
|
|
PAINT PINK (340 630);
|
|
DISPLAY INVISIBLE (340 630);
|
|
FORCEPROP 1 LASTPIN (325 700) HDL_PORT OUT
|
|
J 0
|
|
(700 575);
|
|
DISPLAY 0.872340 (700 575);
|
|
PAINT ORANGE (700 575);
|
|
DISPLAY INVISIBLE (700 575);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(700 575);
|
|
DISPLAY 0.872340 (700 575);
|
|
PAINT ORANGE (700 575);
|
|
DISPLAY INVISIBLE (700 575);
|
|
FORCEPROP 1 LAST PATH I63
|
|
J 0
|
|
(375 750);
|
|
DISPLAY 0.872340 (375 750);
|
|
PAINT PINK (375 750);
|
|
DISPLAY INVISIBLE (375 750);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(375 700);
|
|
DISPLAY INVISIBLE (375 700);
|
|
FORCEADD OUTPORT..1
|
|
(375 625);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(375 625);
|
|
DISPLAY INVISIBLE (375 625);
|
|
FORCEPROP 1 LAST PATH I64
|
|
J 0
|
|
(375 675);
|
|
DISPLAY 0.872340 (375 675);
|
|
PAINT PINK (375 675);
|
|
DISPLAY INVISIBLE (375 675);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(700 500);
|
|
DISPLAY 0.872340 (700 500);
|
|
PAINT ORANGE (700 500);
|
|
DISPLAY INVISIBLE (700 500);
|
|
FORCEPROP 1 LASTPIN (325 625) HDL_PORT OUT
|
|
J 0
|
|
(700 500);
|
|
DISPLAY 0.872340 (700 500);
|
|
PAINT ORANGE (700 500);
|
|
DISPLAY INVISIBLE (700 500);
|
|
FORCEPROP 1 LASTPIN (325 625) VHDL_PORT OUT
|
|
J 0
|
|
(340 555);
|
|
DISPLAY 0.872340 (340 555);
|
|
PAINT PINK (340 555);
|
|
DISPLAY INVISIBLE (340 555);
|
|
FORCEADD INPORT..1
|
|
(-1725 1000);
|
|
FORCEPROP 2 LASTPIN (-1675 1000) SIG_NAME MTCA_MIMIC1_PULSE_ANAL
|
|
J 0
|
|
(-1685 1035);
|
|
DISPLAY 1.021277 (-1685 1035);
|
|
PAINT ORANGE (-1685 1035);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1725 1000);
|
|
DISPLAY INVISIBLE (-1725 1000);
|
|
FORCEPROP 1 LAST PATH I65
|
|
J 0
|
|
(-1750 1050);
|
|
DISPLAY 0.872340 (-1750 1050);
|
|
PAINT PINK (-1750 1050);
|
|
DISPLAY INVISIBLE (-1750 1050);
|
|
FORCEPROP 1 LASTPIN (-1675 1000) VHDL_PORT IN
|
|
J 0
|
|
(-1660 930);
|
|
DISPLAY 0.872340 (-1660 930);
|
|
PAINT PINK (-1660 930);
|
|
DISPLAY INVISIBLE (-1660 930);
|
|
FORCEPROP 1 LASTPIN (-1675 1000) HDL_PORT IN
|
|
J 0
|
|
(-1400 875);
|
|
DISPLAY 0.872340 (-1400 875);
|
|
PAINT ORANGE (-1400 875);
|
|
DISPLAY INVISIBLE (-1400 875);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1400 875);
|
|
DISPLAY 0.872340 (-1400 875);
|
|
PAINT ORANGE (-1400 875);
|
|
DISPLAY INVISIBLE (-1400 875);
|
|
FORCEADD INPORT..1
|
|
(-1725 875);
|
|
FORCEPROP 1 LASTPIN (-1675 875) VHDL_PORT IN
|
|
J 0
|
|
(-1660 805);
|
|
DISPLAY 0.872340 (-1660 805);
|
|
PAINT PINK (-1660 805);
|
|
DISPLAY INVISIBLE (-1660 805);
|
|
FORCEPROP 1 LASTPIN (-1675 875) HDL_PORT IN
|
|
J 0
|
|
(-1400 750);
|
|
DISPLAY 0.872340 (-1400 750);
|
|
PAINT ORANGE (-1400 750);
|
|
DISPLAY INVISIBLE (-1400 750);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1400 750);
|
|
DISPLAY 0.872340 (-1400 750);
|
|
PAINT ORANGE (-1400 750);
|
|
DISPLAY INVISIBLE (-1400 750);
|
|
FORCEPROP 1 LAST PATH I66
|
|
J 0
|
|
(-1750 925);
|
|
DISPLAY 0.872340 (-1750 925);
|
|
PAINT PINK (-1750 925);
|
|
DISPLAY INVISIBLE (-1750 925);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1725 875);
|
|
DISPLAY INVISIBLE (-1725 875);
|
|
FORCEADD INPORT..1
|
|
(-4175 4300);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4175 4300);
|
|
DISPLAY INVISIBLE (-4175 4300);
|
|
FORCEPROP 1 LAST PATH I67
|
|
J 0
|
|
(-4200 4350);
|
|
DISPLAY 0.872340 (-4200 4350);
|
|
PAINT PINK (-4200 4350);
|
|
DISPLAY INVISIBLE (-4200 4350);
|
|
FORCEPROP 1 LASTPIN (-4125 4300) HDL_PORT IN
|
|
J 0
|
|
(-3850 4175);
|
|
DISPLAY 0.872340 (-3850 4175);
|
|
PAINT ORANGE (-3850 4175);
|
|
DISPLAY INVISIBLE (-3850 4175);
|
|
FORCEPROP 1 LASTPIN (-4125 4300) VHDL_PORT IN
|
|
J 0
|
|
(-4110 4230);
|
|
DISPLAY 0.872340 (-4110 4230);
|
|
PAINT PINK (-4110 4230);
|
|
DISPLAY INVISIBLE (-4110 4230);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3850 4175);
|
|
DISPLAY 0.872340 (-3850 4175);
|
|
PAINT ORANGE (-3850 4175);
|
|
DISPLAY INVISIBLE (-3850 4175);
|
|
FORCEADD OUTPORT..1
|
|
(-2100 4525);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-2100 4525);
|
|
DISPLAY INVISIBLE (-2100 4525);
|
|
FORCEPROP 1 LAST PATH I68
|
|
J 0
|
|
(-2100 4575);
|
|
DISPLAY 0.872340 (-2100 4575);
|
|
PAINT PINK (-2100 4575);
|
|
DISPLAY INVISIBLE (-2100 4575);
|
|
FORCEPROP 1 LASTPIN (-2150 4525) VHDL_PORT OUT
|
|
J 0
|
|
(-2135 4455);
|
|
DISPLAY 0.872340 (-2135 4455);
|
|
PAINT PINK (-2135 4455);
|
|
DISPLAY INVISIBLE (-2135 4455);
|
|
FORCEPROP 1 LASTPIN (-2150 4525) HDL_PORT OUT
|
|
J 0
|
|
(-1775 4400);
|
|
DISPLAY 0.872340 (-1775 4400);
|
|
PAINT ORANGE (-1775 4400);
|
|
DISPLAY INVISIBLE (-1775 4400);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1775 4400);
|
|
DISPLAY 0.872340 (-1775 4400);
|
|
PAINT ORANGE (-1775 4400);
|
|
DISPLAY INVISIBLE (-1775 4400);
|
|
FORCEADD OUTPORT..1
|
|
(-2100 4600);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-2100 4600);
|
|
DISPLAY INVISIBLE (-2100 4600);
|
|
FORCEPROP 1 LAST PATH I69
|
|
J 0
|
|
(-2100 4650);
|
|
DISPLAY 0.872340 (-2100 4650);
|
|
PAINT PINK (-2100 4650);
|
|
DISPLAY INVISIBLE (-2100 4650);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1775 4475);
|
|
DISPLAY 0.872340 (-1775 4475);
|
|
PAINT ORANGE (-1775 4475);
|
|
DISPLAY INVISIBLE (-1775 4475);
|
|
FORCEPROP 1 LASTPIN (-2150 4600) HDL_PORT OUT
|
|
J 0
|
|
(-1775 4475);
|
|
DISPLAY 0.872340 (-1775 4475);
|
|
PAINT ORANGE (-1775 4475);
|
|
DISPLAY INVISIBLE (-1775 4475);
|
|
FORCEPROP 1 LASTPIN (-2150 4600) VHDL_PORT OUT
|
|
J 0
|
|
(-2135 4530);
|
|
DISPLAY 0.872340 (-2135 4530);
|
|
PAINT PINK (-2135 4530);
|
|
DISPLAY INVISIBLE (-2135 4530);
|
|
FORCEADD EXT_TRIGS..1
|
|
(-2575 1200);
|
|
FORCEPROP 2 LASTPIN (-2175 1200) SIG_NAME UN$1$EXTTRIGS$I70$EXTTRIGOUT
|
|
J 0
|
|
(-2165 1210);
|
|
DISPLAY 0.659574 (-2165 1210);
|
|
PAINT MONO (-2165 1210);
|
|
DISPLAY INVISIBLE (-2165 1210);
|
|
FORCEPROP 2 LAST PATH I70
|
|
J 0
|
|
(-2375 1625);
|
|
DISPLAY 1.021277 (-2375 1625);
|
|
PAINT ORANGE (-2375 1625);
|
|
FORCEPROP 1 LASTPIN (-2175 1200) VHDL_MODE OUT
|
|
J 0
|
|
(-2155 1133);
|
|
DISPLAY INVISIBLE (-2155 1133);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(-2575 1210);
|
|
DISPLAY INVISIBLE (-2575 1210);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-2575 1200);
|
|
DISPLAY INVISIBLE (-2575 1200);
|
|
FORCEPROP 1 LASTPIN (-3000 1300) VHDL_MODE IN
|
|
J 2
|
|
(-3020 1233);
|
|
DISPLAY INVISIBLE (-3020 1233);
|
|
FORCEADD INPORT..1
|
|
(-3725 1650);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-3725 1650);
|
|
DISPLAY INVISIBLE (-3725 1650);
|
|
FORCEPROP 1 LAST PATH I71
|
|
J 0
|
|
(-3750 1700);
|
|
DISPLAY 0.872340 (-3750 1700);
|
|
PAINT PINK (-3750 1700);
|
|
DISPLAY INVISIBLE (-3750 1700);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3400 1525);
|
|
DISPLAY 0.872340 (-3400 1525);
|
|
PAINT ORANGE (-3400 1525);
|
|
DISPLAY INVISIBLE (-3400 1525);
|
|
FORCEPROP 1 LASTPIN (-3675 1650) HDL_PORT IN
|
|
J 0
|
|
(-3400 1525);
|
|
DISPLAY 0.872340 (-3400 1525);
|
|
PAINT ORANGE (-3400 1525);
|
|
DISPLAY INVISIBLE (-3400 1525);
|
|
FORCEPROP 1 LASTPIN (-3675 1650) VHDL_PORT IN
|
|
J 0
|
|
(-3660 1580);
|
|
DISPLAY 0.872340 (-3660 1580);
|
|
PAINT PINK (-3660 1580);
|
|
DISPLAY INVISIBLE (-3660 1580);
|
|
FORCEADD OUTPORT..1
|
|
(500 4575);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(500 4575);
|
|
DISPLAY INVISIBLE (500 4575);
|
|
FORCEPROP 1 LAST PATH I72
|
|
J 0
|
|
(500 4625);
|
|
DISPLAY 0.872340 (500 4625);
|
|
PAINT PINK (500 4625);
|
|
DISPLAY INVISIBLE (500 4625);
|
|
FORCEPROP 1 LASTPIN (450 4575) VHDL_PORT OUT
|
|
J 0
|
|
(465 4505);
|
|
DISPLAY 0.872340 (465 4505);
|
|
PAINT PINK (465 4505);
|
|
DISPLAY INVISIBLE (465 4505);
|
|
FORCEPROP 1 LASTPIN (450 4575) HDL_PORT OUT
|
|
J 0
|
|
(825 4450);
|
|
DISPLAY 0.872340 (825 4450);
|
|
PAINT ORANGE (825 4450);
|
|
DISPLAY INVISIBLE (825 4450);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(825 4450);
|
|
DISPLAY 0.872340 (825 4450);
|
|
PAINT ORANGE (825 4450);
|
|
DISPLAY INVISIBLE (825 4450);
|
|
FORCEADD OUTPORT..1
|
|
(500 4500);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(500 4500);
|
|
DISPLAY INVISIBLE (500 4500);
|
|
FORCEPROP 1 LAST PATH I73
|
|
J 0
|
|
(500 4550);
|
|
DISPLAY 0.872340 (500 4550);
|
|
PAINT PINK (500 4550);
|
|
DISPLAY INVISIBLE (500 4550);
|
|
FORCEPROP 1 LASTPIN (450 4500) VHDL_PORT OUT
|
|
J 0
|
|
(465 4430);
|
|
DISPLAY 0.872340 (465 4430);
|
|
PAINT PINK (465 4430);
|
|
DISPLAY INVISIBLE (465 4430);
|
|
FORCEPROP 1 LASTPIN (450 4500) HDL_PORT OUT
|
|
J 0
|
|
(825 4375);
|
|
DISPLAY 0.872340 (825 4375);
|
|
PAINT ORANGE (825 4375);
|
|
DISPLAY INVISIBLE (825 4375);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(825 4375);
|
|
DISPLAY 0.872340 (825 4375);
|
|
PAINT ORANGE (825 4375);
|
|
DISPLAY INVISIBLE (825 4375);
|
|
FORCEADD OUTPORT..1
|
|
(500 4425);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(500 4425);
|
|
DISPLAY INVISIBLE (500 4425);
|
|
FORCEPROP 1 LAST PATH I74
|
|
J 0
|
|
(500 4475);
|
|
DISPLAY 0.872340 (500 4475);
|
|
PAINT PINK (500 4475);
|
|
DISPLAY INVISIBLE (500 4475);
|
|
FORCEPROP 1 LASTPIN (450 4425) VHDL_PORT OUT
|
|
J 0
|
|
(465 4355);
|
|
DISPLAY 0.872340 (465 4355);
|
|
PAINT PINK (465 4355);
|
|
DISPLAY INVISIBLE (465 4355);
|
|
FORCEPROP 1 LASTPIN (450 4425) HDL_PORT OUT
|
|
J 0
|
|
(825 4300);
|
|
DISPLAY 0.872340 (825 4300);
|
|
PAINT ORANGE (825 4300);
|
|
DISPLAY INVISIBLE (825 4300);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(825 4300);
|
|
DISPLAY 0.872340 (825 4300);
|
|
PAINT ORANGE (825 4300);
|
|
DISPLAY INVISIBLE (825 4300);
|
|
FORCEADD OUTPORT..1
|
|
(500 4350);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(500 4350);
|
|
DISPLAY INVISIBLE (500 4350);
|
|
FORCEPROP 1 LAST PATH I75
|
|
J 0
|
|
(500 4400);
|
|
DISPLAY 0.872340 (500 4400);
|
|
PAINT PINK (500 4400);
|
|
DISPLAY INVISIBLE (500 4400);
|
|
FORCEPROP 1 LASTPIN (450 4350) VHDL_PORT OUT
|
|
J 0
|
|
(465 4280);
|
|
DISPLAY 0.872340 (465 4280);
|
|
PAINT PINK (465 4280);
|
|
DISPLAY INVISIBLE (465 4280);
|
|
FORCEPROP 1 LASTPIN (450 4350) HDL_PORT OUT
|
|
J 0
|
|
(825 4225);
|
|
DISPLAY 0.872340 (825 4225);
|
|
PAINT ORANGE (825 4225);
|
|
DISPLAY INVISIBLE (825 4225);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(825 4225);
|
|
DISPLAY 0.872340 (825 4225);
|
|
PAINT ORANGE (825 4225);
|
|
DISPLAY INVISIBLE (825 4225);
|
|
FORCEADD INPORT..1
|
|
(-1850 4550);
|
|
FORCEPROP 2 LASTPIN (-1800 4550) SIG_NAME SMELLIE_DELAY_IN
|
|
J 0
|
|
(-1785 4585);
|
|
DISPLAY 1.021277 (-1785 4585);
|
|
PAINT ORANGE (-1785 4585);
|
|
FORCEPROP 1 LASTPIN (-1800 4550) VHDL_PORT IN
|
|
J 0
|
|
(-1785 4480);
|
|
DISPLAY 0.872340 (-1785 4480);
|
|
PAINT PINK (-1785 4480);
|
|
DISPLAY INVISIBLE (-1785 4480);
|
|
FORCEPROP 1 LASTPIN (-1800 4550) HDL_PORT IN
|
|
J 0
|
|
(-1525 4425);
|
|
DISPLAY 0.872340 (-1525 4425);
|
|
PAINT ORANGE (-1525 4425);
|
|
DISPLAY INVISIBLE (-1525 4425);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1525 4425);
|
|
DISPLAY 0.872340 (-1525 4425);
|
|
PAINT ORANGE (-1525 4425);
|
|
DISPLAY INVISIBLE (-1525 4425);
|
|
FORCEPROP 1 LAST PATH I76
|
|
J 0
|
|
(-1875 4600);
|
|
DISPLAY 0.872340 (-1875 4600);
|
|
PAINT PINK (-1875 4600);
|
|
DISPLAY INVISIBLE (-1875 4600);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1850 4550);
|
|
DISPLAY INVISIBLE (-1850 4550);
|
|
FORCEADD INPORT..1
|
|
(-1850 4475);
|
|
FORCEPROP 1 LASTPIN (-1800 4475) VHDL_PORT IN
|
|
J 0
|
|
(-1785 4405);
|
|
DISPLAY 0.872340 (-1785 4405);
|
|
PAINT PINK (-1785 4405);
|
|
DISPLAY INVISIBLE (-1785 4405);
|
|
FORCEPROP 1 LASTPIN (-1800 4475) HDL_PORT IN
|
|
J 0
|
|
(-1525 4350);
|
|
DISPLAY 0.872340 (-1525 4350);
|
|
PAINT ORANGE (-1525 4350);
|
|
DISPLAY INVISIBLE (-1525 4350);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-1525 4350);
|
|
DISPLAY 0.872340 (-1525 4350);
|
|
PAINT ORANGE (-1525 4350);
|
|
DISPLAY INVISIBLE (-1525 4350);
|
|
FORCEPROP 1 LAST PATH I77
|
|
J 0
|
|
(-1875 4525);
|
|
DISPLAY 0.872340 (-1875 4525);
|
|
PAINT PINK (-1875 4525);
|
|
DISPLAY INVISIBLE (-1875 4525);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-1850 4475);
|
|
DISPLAY INVISIBLE (-1850 4475);
|
|
FORCEADD OUTPORT..1
|
|
(2925 4150);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(2925 4150);
|
|
DISPLAY INVISIBLE (2925 4150);
|
|
FORCEPROP 1 LAST PATH I78
|
|
J 0
|
|
(2925 4200);
|
|
DISPLAY 0.872340 (2925 4200);
|
|
PAINT PINK (2925 4200);
|
|
DISPLAY INVISIBLE (2925 4200);
|
|
FORCEPROP 1 LASTPIN (2875 4150) VHDL_PORT OUT
|
|
J 0
|
|
(2890 4080);
|
|
DISPLAY 0.872340 (2890 4080);
|
|
PAINT PINK (2890 4080);
|
|
DISPLAY INVISIBLE (2890 4080);
|
|
FORCEPROP 1 LASTPIN (2875 4150) HDL_PORT OUT
|
|
J 0
|
|
(3250 4025);
|
|
DISPLAY 0.872340 (3250 4025);
|
|
PAINT ORANGE (3250 4025);
|
|
DISPLAY INVISIBLE (3250 4025);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3250 4025);
|
|
DISPLAY 0.872340 (3250 4025);
|
|
PAINT ORANGE (3250 4025);
|
|
DISPLAY INVISIBLE (3250 4025);
|
|
FORCEADD OUTPORT..1
|
|
(575 1875);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(575 1875);
|
|
DISPLAY INVISIBLE (575 1875);
|
|
FORCEPROP 1 LAST PATH I79
|
|
J 0
|
|
(575 1925);
|
|
DISPLAY 0.872340 (575 1925);
|
|
PAINT PINK (575 1925);
|
|
DISPLAY INVISIBLE (575 1925);
|
|
FORCEPROP 1 LASTPIN (525 1875) VHDL_PORT OUT
|
|
J 0
|
|
(540 1805);
|
|
DISPLAY 0.872340 (540 1805);
|
|
PAINT PINK (540 1805);
|
|
DISPLAY INVISIBLE (540 1805);
|
|
FORCEPROP 1 LASTPIN (525 1875) HDL_PORT OUT
|
|
J 0
|
|
(900 1750);
|
|
DISPLAY 0.872340 (900 1750);
|
|
PAINT ORANGE (900 1750);
|
|
DISPLAY INVISIBLE (900 1750);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(900 1750);
|
|
DISPLAY 0.872340 (900 1750);
|
|
PAINT ORANGE (900 1750);
|
|
DISPLAY INVISIBLE (900 1750);
|
|
FORCEADD CAEN_COMS..1
|
|
(2050 3100);
|
|
FORCEPROP 2 LASTPIN (2550 3200) SIG_NAME UN$1$CAENCOMS$I8$GTTTL
|
|
J 0
|
|
(2560 3210);
|
|
DISPLAY 0.659574 (2560 3210);
|
|
PAINT MONO (2560 3210);
|
|
DISPLAY INVISIBLE (2560 3210);
|
|
FORCEPROP 2 LASTPIN (2550 2850) SIG_NAME UN$1$CAENCOMS$I8$SYNCTTL
|
|
J 0
|
|
(2560 2860);
|
|
DISPLAY 0.659574 (2560 2860);
|
|
PAINT MONO (2560 2860);
|
|
DISPLAY INVISIBLE (2560 2860);
|
|
FORCEPROP 2 LASTPIN (2550 2775) SIG_NAME UN$1$CAENCOMS$I8$SYNC24TTL
|
|
J 0
|
|
(2560 2785);
|
|
DISPLAY 0.659574 (2560 2785);
|
|
PAINT MONO (2560 2785);
|
|
DISPLAY INVISIBLE (2560 2785);
|
|
FORCEPROP 2 LASTPIN (1450 2800) SIG_NAME UN$1$CAENCOMS$I8$DATARDY
|
|
J 0
|
|
(1460 2810);
|
|
DISPLAY 0.659574 (1460 2810);
|
|
PAINT MONO (1460 2810);
|
|
DISPLAY INVISIBLE (1460 2810);
|
|
FORCEPROP 2 LASTPIN (2550 3100) SIG_NAME UN$1$CAENCOMS$I8$GT2P
|
|
J 0
|
|
(2560 3110);
|
|
DISPLAY 0.659574 (2560 3110);
|
|
PAINT MONO (2560 3110);
|
|
DISPLAY INVISIBLE (2560 3110);
|
|
FORCEPROP 2 LAST PATH I8
|
|
J 0
|
|
(2400 3650);
|
|
DISPLAY 1.021277 (2400 3650);
|
|
PAINT ORANGE (2400 3650);
|
|
FORCEPROP 1 LASTPIN (1450 3125) VHDL_MODE IN
|
|
J 2
|
|
(1430 3058);
|
|
DISPLAY INVISIBLE (1430 3058);
|
|
FORCEPROP 1 LASTPIN (2550 2775) VHDL_MODE OUT
|
|
J 0
|
|
(2570 2708);
|
|
DISPLAY INVISIBLE (2570 2708);
|
|
FORCEPROP 1 LASTPIN (2550 2850) VHDL_MODE OUT
|
|
J 0
|
|
(2570 2783);
|
|
DISPLAY INVISIBLE (2570 2783);
|
|
FORCEPROP 1 LASTPIN (2550 3200) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3133);
|
|
DISPLAY INVISIBLE (2570 3133);
|
|
FORCEPROP 1 LASTPIN (2550 3275) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3208);
|
|
DISPLAY INVISIBLE (2570 3208);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(2050 3110);
|
|
DISPLAY INVISIBLE (2050 3110);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(2050 3100);
|
|
DISPLAY INVISIBLE (2050 3100);
|
|
FORCEPROP 1 LASTPIN (1450 3650) VHDL_MODE IN
|
|
J 2
|
|
(1430 3583);
|
|
DISPLAY INVISIBLE (1430 3583);
|
|
FORCEPROP 1 LASTPIN (1450 3600) VHDL_MODE IN
|
|
J 2
|
|
(1430 3533);
|
|
DISPLAY INVISIBLE (1430 3533);
|
|
FORCEPROP 1 LASTPIN (1450 3475) VHDL_MODE IN
|
|
J 2
|
|
(1430 3408);
|
|
DISPLAY INVISIBLE (1430 3408);
|
|
FORCEPROP 1 LASTPIN (1450 3275) VHDL_MODE IN
|
|
J 2
|
|
(1430 3208);
|
|
DISPLAY INVISIBLE (1430 3208);
|
|
FORCEPROP 1 LASTPIN (1450 3200) VHDL_MODE IN
|
|
J 2
|
|
(1430 3133);
|
|
DISPLAY INVISIBLE (1430 3133);
|
|
FORCEPROP 1 LASTPIN (1450 3425) VHDL_MODE IN
|
|
J 2
|
|
(1430 3358);
|
|
DISPLAY INVISIBLE (1430 3358);
|
|
FORCEPROP 1 LASTPIN (1450 2975) VHDL_MODE IN
|
|
J 2
|
|
(1430 2908);
|
|
DISPLAY INVISIBLE (1430 2908);
|
|
FORCEPROP 1 LASTPIN (1450 2925) VHDL_MODE IN
|
|
J 2
|
|
(1430 2858);
|
|
DISPLAY INVISIBLE (1430 2858);
|
|
FORCEPROP 1 LASTPIN (1450 2875) VHDL_MODE IN
|
|
J 2
|
|
(1430 2808);
|
|
DISPLAY INVISIBLE (1430 2808);
|
|
FORCEPROP 1 LASTPIN (1450 2800) VHDL_MODE IN
|
|
J 2
|
|
(1430 2733);
|
|
DISPLAY INVISIBLE (1430 2733);
|
|
FORCEPROP 1 LASTPIN (2550 3600) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3533);
|
|
DISPLAY INVISIBLE (2570 3533);
|
|
FORCEPROP 1 LASTPIN (2550 3525) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3458);
|
|
DISPLAY INVISIBLE (2570 3458);
|
|
FORCEPROP 1 LASTPIN (2550 3425) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3358);
|
|
DISPLAY INVISIBLE (2570 3358);
|
|
FORCEPROP 1 LASTPIN (2550 3375) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3308);
|
|
DISPLAY INVISIBLE (2570 3308);
|
|
FORCEPROP 1 LASTPIN (2550 2925) VHDL_MODE OUT
|
|
J 0
|
|
(2570 2858);
|
|
DISPLAY INVISIBLE (2570 2858);
|
|
FORCEPROP 1 LASTPIN (2550 2975) VHDL_MODE OUT
|
|
J 0
|
|
(2570 2908);
|
|
DISPLAY INVISIBLE (2570 2908);
|
|
FORCEPROP 1 LASTPIN (2550 3100) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3033);
|
|
DISPLAY INVISIBLE (2570 3033);
|
|
FORCEPROP 1 LASTPIN (2550 3050) VHDL_MODE OUT
|
|
J 0
|
|
(2570 2983);
|
|
DISPLAY INVISIBLE (2570 2983);
|
|
FORCEPROP 1 LASTPIN (2550 3150) VHDL_MODE OUT
|
|
J 0
|
|
(2570 3083);
|
|
DISPLAY INVISIBLE (2570 3083);
|
|
FORCEADD OUTPORT..1
|
|
R 2
|
|
(-1675 2100);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 2
|
|
(-2000 1975);
|
|
DISPLAY 0.872340 (-2000 1975);
|
|
PAINT ORANGE (-2000 1975);
|
|
DISPLAY INVISIBLE (-2000 1975);
|
|
FORCEPROP 1 LASTPIN (-1625 2100) HDL_PORT OUT
|
|
J 2
|
|
(-2000 1975);
|
|
DISPLAY 0.872340 (-2000 1975);
|
|
PAINT ORANGE (-2000 1975);
|
|
DISPLAY INVISIBLE (-2000 1975);
|
|
FORCEPROP 1 LASTPIN (-1625 2100) VHDL_PORT OUT
|
|
J 2
|
|
(-1640 2030);
|
|
DISPLAY 0.872340 (-1640 2030);
|
|
PAINT PINK (-1640 2030);
|
|
DISPLAY INVISIBLE (-1640 2030);
|
|
FORCEPROP 1 LAST PATH I80
|
|
J 2
|
|
(-1675 2150);
|
|
DISPLAY 0.872340 (-1675 2150);
|
|
PAINT PINK (-1675 2150);
|
|
DISPLAY INVISIBLE (-1675 2150);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 2
|
|
(-1675 2100);
|
|
DISPLAY INVISIBLE (-1675 2100);
|
|
FORCEADD INPORT..1
|
|
(-4175 4250);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(-3850 4125);
|
|
DISPLAY 0.872340 (-3850 4125);
|
|
PAINT ORANGE (-3850 4125);
|
|
DISPLAY INVISIBLE (-3850 4125);
|
|
FORCEPROP 1 LASTPIN (-4125 4250) HDL_PORT IN
|
|
J 0
|
|
(-3850 4125);
|
|
DISPLAY 0.872340 (-3850 4125);
|
|
PAINT ORANGE (-3850 4125);
|
|
DISPLAY INVISIBLE (-3850 4125);
|
|
FORCEPROP 1 LASTPIN (-4125 4250) VHDL_PORT IN
|
|
J 0
|
|
(-4110 4180);
|
|
DISPLAY 0.872340 (-4110 4180);
|
|
PAINT PINK (-4110 4180);
|
|
DISPLAY INVISIBLE (-4110 4180);
|
|
FORCEPROP 1 LAST PATH I81
|
|
J 0
|
|
(-4200 4300);
|
|
DISPLAY 0.872340 (-4200 4300);
|
|
PAINT PINK (-4200 4300);
|
|
DISPLAY INVISIBLE (-4200 4300);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-4175 4250);
|
|
DISPLAY INVISIBLE (-4175 4250);
|
|
FORCEADD FAN_CONNECTIONS..1
|
|
(-3900 1050);
|
|
FORCEPROP 2 LAST PATH I82
|
|
J 0
|
|
(-3675 1475);
|
|
DISPLAY 1.021277 (-3675 1475);
|
|
PAINT ORANGE (-3675 1475);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-3900 1050);
|
|
DISPLAY INVISIBLE (-3900 1050);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(-3900 1060);
|
|
DISPLAY INVISIBLE (-3900 1060);
|
|
FORCEADD OUTPORT..1
|
|
(3225 3150);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 0
|
|
(3550 3025);
|
|
DISPLAY 0.872340 (3550 3025);
|
|
PAINT ORANGE (3550 3025);
|
|
DISPLAY INVISIBLE (3550 3025);
|
|
FORCEPROP 1 LASTPIN (3175 3150) HDL_PORT OUT
|
|
J 0
|
|
(3550 3025);
|
|
DISPLAY 0.872340 (3550 3025);
|
|
PAINT ORANGE (3550 3025);
|
|
DISPLAY INVISIBLE (3550 3025);
|
|
FORCEPROP 1 LASTPIN (3175 3150) VHDL_PORT OUT
|
|
J 0
|
|
(3190 3080);
|
|
DISPLAY 0.872340 (3190 3080);
|
|
PAINT PINK (3190 3080);
|
|
DISPLAY INVISIBLE (3190 3080);
|
|
FORCEPROP 1 LAST PATH I83
|
|
J 0
|
|
(3225 3200);
|
|
DISPLAY 0.872340 (3225 3200);
|
|
PAINT PINK (3225 3200);
|
|
DISPLAY INVISIBLE (3225 3200);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(3225 3150);
|
|
DISPLAY INVISIBLE (3225 3150);
|
|
FORCEADD OUTPORT..1
|
|
R 2
|
|
(-2000 2200);
|
|
FORCEPROP 2 LAST CDS_LIB standard
|
|
J 0
|
|
(-2000 2200);
|
|
DISPLAY INVISIBLE (-2000 2200);
|
|
FORCEPROP 1 LAST PATH I84
|
|
J 2
|
|
(-2000 2250);
|
|
DISPLAY 0.872340 (-2000 2250);
|
|
PAINT PINK (-2000 2250);
|
|
DISPLAY INVISIBLE (-2000 2250);
|
|
FORCEPROP 1 LASTPIN (-1950 2200) VHDL_PORT OUT
|
|
J 2
|
|
(-1965 2130);
|
|
DISPLAY 0.872340 (-1965 2130);
|
|
PAINT PINK (-1965 2130);
|
|
DISPLAY INVISIBLE (-1965 2130);
|
|
FORCEPROP 1 LASTPIN (-1950 2200) HDL_PORT OUT
|
|
J 2
|
|
(-2325 2075);
|
|
DISPLAY 0.872340 (-2325 2075);
|
|
PAINT ORANGE (-2325 2075);
|
|
DISPLAY INVISIBLE (-2325 2075);
|
|
FORCEPROP 1 LAST OFFPAGE TRUE
|
|
J 2
|
|
(-2325 2075);
|
|
DISPLAY 0.872340 (-2325 2075);
|
|
PAINT ORANGE (-2325 2075);
|
|
DISPLAY INVISIBLE (-2325 2075);
|
|
FORCEADD ELLIE_COMS..1
|
|
(-475 4375);
|
|
FORCEPROP 2 LASTPIN (-1400 4300) SIG_NAME UN$1$ELLIECOMS$I9$SMELLIEDELAYOUTTTL
|
|
J 0
|
|
(-1390 4310);
|
|
DISPLAY 0.659574 (-1390 4310);
|
|
PAINT MONO (-1390 4310);
|
|
DISPLAY INVISIBLE (-1390 4310);
|
|
FORCEPROP 2 LASTPIN (-1400 4200) SIG_NAME UN$1$ELLIECOMS$I9$TELLIEDELAYOUTTTL
|
|
J 0
|
|
(-1390 4210);
|
|
DISPLAY 0.659574 (-1390 4210);
|
|
PAINT MONO (-1390 4210);
|
|
DISPLAY INVISIBLE (-1390 4210);
|
|
FORCEPROP 2 LASTPIN (-1400 4775) SIG_NAME UN$1$ELLIECOMS$I9$SMELLIEPULSE
|
|
J 0
|
|
(-1390 4785);
|
|
DISPLAY 0.659574 (-1390 4785);
|
|
PAINT MONO (-1390 4785);
|
|
DISPLAY INVISIBLE (-1390 4785);
|
|
FORCEPROP 2 LASTPIN (-1400 4700) SIG_NAME UN$1$ELLIECOMS$I9$TELLIEPULSE
|
|
J 0
|
|
(-1390 4710);
|
|
DISPLAY 0.659574 (-1390 4710);
|
|
PAINT MONO (-1390 4710);
|
|
DISPLAY INVISIBLE (-1390 4710);
|
|
FORCEPROP 2 LASTPIN (75 4175) SIG_NAME UN$1$ELLIECOMS$I9$TELLIEPREDELAYTTL
|
|
J 0
|
|
(85 4185);
|
|
DISPLAY 0.659574 (85 4185);
|
|
PAINT MONO (85 4185);
|
|
DISPLAY INVISIBLE (85 4185);
|
|
FORCEPROP 2 LASTPIN (75 4275) SIG_NAME UN$1$ELLIECOMS$I9$SMELLIEPREDELAYTTL
|
|
J 0
|
|
(85 4285);
|
|
DISPLAY 0.659574 (85 4285);
|
|
PAINT MONO (85 4285);
|
|
DISPLAY INVISIBLE (85 4285);
|
|
FORCEPROP 2 LAST PATH I9
|
|
J 0
|
|
(-175 4875);
|
|
DISPLAY 1.021277 (-175 4875);
|
|
PAINT ORANGE (-175 4875);
|
|
FORCEPROP 1 LAST BLOCK TRUE
|
|
J 1
|
|
(-475 4385);
|
|
DISPLAY INVISIBLE (-475 4385);
|
|
FORCEPROP 2 LAST CDS_LIB tubii_tk2_lib
|
|
J 0
|
|
(-475 4375);
|
|
DISPLAY INVISIBLE (-475 4375);
|
|
FORCEPROP 1 LASTPIN (75 4575) VHDL_MODE OUT
|
|
J 0
|
|
(95 4508);
|
|
DISPLAY INVISIBLE (95 4508);
|
|
FORCEPROP 1 LASTPIN (75 4500) VHDL_MODE OUT
|
|
J 0
|
|
(95 4433);
|
|
DISPLAY INVISIBLE (95 4433);
|
|
FORCEPROP 1 LASTPIN (75 4425) VHDL_MODE OUT
|
|
J 0
|
|
(95 4358);
|
|
DISPLAY INVISIBLE (95 4358);
|
|
FORCEPROP 1 LASTPIN (75 4350) VHDL_MODE OUT
|
|
J 0
|
|
(95 4283);
|
|
DISPLAY INVISIBLE (95 4283);
|
|
FORCEPROP 1 LASTPIN (-1400 4550) VHDL_MODE IN
|
|
J 2
|
|
(-1420 4483);
|
|
DISPLAY INVISIBLE (-1420 4483);
|
|
FORCEPROP 1 LASTPIN (-1400 4475) VHDL_MODE IN
|
|
J 2
|
|
(-1420 4408);
|
|
DISPLAY INVISIBLE (-1420 4408);
|
|
FORCEPROP 1 LASTPIN (75 4275) VHDL_MODE OUT
|
|
J 0
|
|
(95 4208);
|
|
DISPLAY INVISIBLE (95 4208);
|
|
FORCEPROP 1 LASTPIN (75 4175) VHDL_MODE OUT
|
|
J 0
|
|
(95 4108);
|
|
DISPLAY INVISIBLE (95 4108);
|
|
FORCEPROP 1 LASTPIN (-1400 4300) VHDL_MODE IN
|
|
J 2
|
|
(-1420 4233);
|
|
DISPLAY INVISIBLE (-1420 4233);
|
|
FORCEPROP 1 LASTPIN (-1400 4200) VHDL_MODE IN
|
|
J 2
|
|
(-1420 4133);
|
|
DISPLAY INVISIBLE (-1420 4133);
|
|
FORCEPROP 1 LASTPIN (-1400 4775) VHDL_MODE IN
|
|
J 2
|
|
(-1420 4708);
|
|
DISPLAY INVISIBLE (-1420 4708);
|
|
FORCEPROP 1 LASTPIN (-1400 4700) VHDL_MODE IN
|
|
J 2
|
|
(-1420 4633);
|
|
DISPLAY INVISIBLE (-1420 4633);
|
|
FORCEADD PENN B SIZE PAGE..1
|
|
(3650 50);
|
|
FORCEPROP 1 LAST COMMENT_BODY TRUE
|
|
J 0
|
|
(1825 -25);
|
|
DISPLAY 0.872340 (1825 -25);
|
|
PAINT WHITE (1825 -25);
|
|
DISPLAY INVISIBLE (1825 -25);
|
|
FORCEPROP 2 LAST CDS_LIB misc
|
|
J 0
|
|
(3650 50);
|
|
DISPLAY INVISIBLE (3650 50);
|
|
WIRE 16 -1 (-4200 2300)(-3525 2300);
|
|
WIRE 17 -1 (-3200 1300)(-3000 1300);
|
|
WIRE 17 -1 (-3200 1650)(-3200 1300);
|
|
WIRE 17 -1 (-3675 1650)(-3200 1650);
|
|
FORCEPROP 2 LAST SIG_NAME EXT_TRIG_IN<0..15>
|
|
J 0
|
|
(-3635 1710);
|
|
DISPLAY 1.021277 (-3635 1710);
|
|
PAINT ORANGE (-3635 1710);
|
|
WIRE 16 -1 (675 4375)(675 2800);
|
|
WIRE 16 -1 (675 2800)(625 2800);
|
|
WIRE 16 -1 (1350 4375)(675 4375);
|
|
FORCEPROP 2 LAST SIG_NAME LE_CNTRL_REG
|
|
J 0
|
|
(840 4385);
|
|
DISPLAY 1.021277 (840 4385);
|
|
PAINT ORANGE (840 4385);
|
|
WIRE 16 -1 (-2600 4600)(-2150 4600);
|
|
FORCEPROP 2 LAST SIG_NAME CLK100_P
|
|
J 0
|
|
(-2560 4635);
|
|
DISPLAY 1.021277 (-2560 4635);
|
|
PAINT ORANGE (-2560 4635);
|
|
WIRE 16 -1 (-2150 4525)(-2600 4525);
|
|
FORCEPROP 2 LAST SIG_NAME CLK100_N
|
|
J 0
|
|
(-2510 4560);
|
|
DISPLAY 1.021277 (-2510 4560);
|
|
PAINT ORANGE (-2510 4560);
|
|
WIRE 16 -1 (-3525 2850)(-4175 2850);
|
|
FORCEPROP 2 LAST SIG_NAME PULSE_INV_IN
|
|
J 0
|
|
(-4135 2860);
|
|
DISPLAY 1.021277 (-4135 2860);
|
|
PAINT ORANGE (-4135 2860);
|
|
WIRE 16 -1 (1050 2650)(1050 2100);
|
|
FORCEPROP 2 LAST SIG_NAME LE_GT_DELAYS
|
|
J 0
|
|
(840 2585);
|
|
DISPLAY 1.021277 (840 2585);
|
|
PAINT ORANGE (840 2585);
|
|
WIRE 16 -1 (1050 2100)(1375 2100);
|
|
WIRE 16 -1 (625 2650)(1050 2650);
|
|
WIRE 16 -1 (-1350 875)(-1675 875);
|
|
FORCEPROP 2 LAST SIG_NAME MTCA_MIMI2_PULSE_ANAL
|
|
J 0
|
|
(-1660 910);
|
|
DISPLAY 1.021277 (-1660 910);
|
|
PAINT ORANGE (-1660 910);
|
|
WIRE 16 -1 (325 350)(0 350);
|
|
FORCEPROP 2 LAST SIG_NAME MTCA_MIMIC2_OUT_N
|
|
J 0
|
|
(15 385);
|
|
DISPLAY 1.021277 (15 385);
|
|
PAINT ORANGE (15 385);
|
|
WIRE 16 -1 (0 450)(325 450);
|
|
FORCEPROP 2 LAST SIG_NAME MTCA_MIMIC2_OUT_P
|
|
J 0
|
|
(-10 485);
|
|
DISPLAY 1.021277 (-10 485);
|
|
PAINT ORANGE (-10 485);
|
|
WIRE 16 -1 (325 625)(0 625);
|
|
WIRE 16 -1 (0 700)(325 700);
|
|
FORCEPROP 2 LAST SIG_NAME MTCA_MIMIC1_OUT_P
|
|
J 0
|
|
(-10 760);
|
|
DISPLAY 1.021277 (-10 760);
|
|
PAINT ORANGE (-10 760);
|
|
WIRE 16 -1 (1050 2875)(1450 2875);
|
|
WIRE 16 -1 (1050 2750)(1050 2875);
|
|
WIRE 16 -1 (625 2750)(1050 2750);
|
|
FORCEPROP 2 LAST SIG_NAME LE_CAEN
|
|
J 0
|
|
(840 2760);
|
|
DISPLAY 1.021277 (840 2760);
|
|
PAINT ORANGE (840 2760);
|
|
WIRE 17 -1 (950 3125)(1450 3125);
|
|
FORCEPROP 2 LAST SIG_NAME PULSE_IN_ANAL<0..11>
|
|
J 0
|
|
(990 3160);
|
|
DISPLAY 1.021277 (990 3160);
|
|
PAINT ORANGE (990 3160);
|
|
WIRE 16 -1 (975 3425)(1450 3425);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_N
|
|
J 0
|
|
(1040 3435);
|
|
DISPLAY 1.021277 (1040 3435);
|
|
PAINT ORANGE (1040 3435);
|
|
WIRE 16 -1 (1000 3275)(1450 3275);
|
|
FORCEPROP 2 LAST SIG_NAME GT_P
|
|
J 0
|
|
(1065 3285);
|
|
DISPLAY 1.021277 (1065 3285);
|
|
PAINT ORANGE (1065 3285);
|
|
WIRE 16 -1 (1450 3600)(975 3600);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_N
|
|
J 0
|
|
(1040 3610);
|
|
DISPLAY 1.021277 (1040 3610);
|
|
PAINT ORANGE (1040 3610);
|
|
WIRE 16 -1 (-4175 2900)(-3525 2900);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_IN_N
|
|
J 0
|
|
(-4210 2910);
|
|
DISPLAY 1.021277 (-4210 2910);
|
|
PAINT ORANGE (-4210 2910);
|
|
WIRE 16 -1 (-3525 2975)(-4175 2975);
|
|
WIRE 16 -1 (-1400 4475)(-1800 4475);
|
|
FORCEPROP 2 LAST SIG_NAME TELLIE_DELAY_IN
|
|
J 0
|
|
(-1785 4510);
|
|
DISPLAY 1.021277 (-1785 4510);
|
|
PAINT ORANGE (-1785 4510);
|
|
WIRE 16 -1 (2550 3275)(3100 3275);
|
|
FORCEPROP 2 LAST SIG_NAME GT_NIM
|
|
J 0
|
|
(2640 3285);
|
|
DISPLAY 1.021277 (2640 3285);
|
|
PAINT ORANGE (2640 3285);
|
|
WIRE 17 -1 (3150 2975)(2550 2975);
|
|
FORCEPROP 2 LAST SIG_NAME SCOPE_OUT_ANAL<0..7>
|
|
J 0
|
|
(2590 2985);
|
|
DISPLAY 1.021277 (2590 2985);
|
|
PAINT ORANGE (2590 2985);
|
|
WIRE 16 -1 (3100 3375)(2550 3375);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_LVDS_N
|
|
J 0
|
|
(2590 3385);
|
|
DISPLAY 1.021277 (2590 3385);
|
|
PAINT ORANGE (2590 3385);
|
|
WIRE 16 -1 (3100 3425)(2550 3425);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_LVDS_P
|
|
J 0
|
|
(2590 3435);
|
|
DISPLAY 1.021277 (2590 3435);
|
|
PAINT ORANGE (2590 3435);
|
|
WIRE 16 -1 (3075 3525)(2550 3525);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_LVDS_N
|
|
J 0
|
|
(2615 3535);
|
|
DISPLAY 1.021277 (2615 3535);
|
|
PAINT ORANGE (2615 3535);
|
|
WIRE 16 -1 (2550 3600)(3075 3600);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_LVDS_P
|
|
J 0
|
|
(2615 3635);
|
|
DISPLAY 1.021277 (2615 3635);
|
|
PAINT ORANGE (2615 3635);
|
|
WIRE 16 -1 (1000 3200)(1450 3200);
|
|
FORCEPROP 2 LAST SIG_NAME GT_N
|
|
J 0
|
|
(1065 3235);
|
|
DISPLAY 1.021277 (1065 3235);
|
|
PAINT ORANGE (1065 3235);
|
|
WIRE 16 -1 (1450 3475)(975 3475);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC24_P
|
|
J 0
|
|
(1040 3485);
|
|
DISPLAY 1.021277 (1040 3485);
|
|
PAINT ORANGE (1040 3485);
|
|
WIRE 16 -1 (975 3650)(1450 3650);
|
|
FORCEPROP 2 LAST SIG_NAME SYNC_P
|
|
J 0
|
|
(1065 3660);
|
|
DISPLAY 1.021277 (1065 3660);
|
|
PAINT ORANGE (1065 3660);
|
|
WIRE 16 -1 (-2150 2350)(-1725 2350);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_LVDS_OUT_N
|
|
J 0
|
|
(-2135 2360);
|
|
DISPLAY 1.021277 (-2135 2360);
|
|
PAINT ORANGE (-2135 2360);
|
|
WIRE 16 -1 (450 4350)(75 4350);
|
|
FORCEPROP 2 LAST SIG_NAME TELLIE_DELAY_OUT
|
|
J 0
|
|
(115 4385);
|
|
DISPLAY 1.021277 (115 4385);
|
|
PAINT ORANGE (115 4385);
|
|
WIRE 16 -1 (75 4425)(450 4425);
|
|
FORCEPROP 2 LAST SIG_NAME SMELLIE_DELAY_OUT
|
|
J 0
|
|
(115 4460);
|
|
DISPLAY 1.021277 (115 4460);
|
|
PAINT ORANGE (115 4460);
|
|
WIRE 16 -1 (450 4500)(75 4500);
|
|
FORCEPROP 2 LAST SIG_NAME TELLIE_PULSE_OUT
|
|
J 0
|
|
(115 4535);
|
|
DISPLAY 1.021277 (115 4535);
|
|
PAINT ORANGE (115 4535);
|
|
WIRE 16 -1 (75 4575)(450 4575);
|
|
FORCEPROP 2 LAST SIG_NAME SMELLIE_PULSE_OUT
|
|
J 0
|
|
(115 4610);
|
|
DISPLAY 1.021277 (115 4610);
|
|
PAINT ORANGE (115 4610);
|
|
WIRE 16 -1 (-1800 4550)(-1400 4550);
|
|
WIRE 16 -1 (-4200 2375)(-3525 2375);
|
|
WIRE 16 -1 (-3525 2450)(-4200 2450);
|
|
WIRE 16 -1 (-4200 2525)(-3525 2525);
|
|
WIRE 16 -1 (-4200 2625)(-3525 2625);
|
|
WIRE 16 -1 (-4200 2675)(-3525 2675);
|
|
WIRE 16 -1 (-3525 2750)(-4200 2750);
|
|
FORCEPROP 2 LAST SIG_NAME TTL_TO_ECL_IN
|
|
J 0
|
|
(-4185 2785);
|
|
DISPLAY 1.021277 (-4185 2785);
|
|
PAINT ORANGE (-4185 2785);
|
|
WIRE 17 -1 (2500 4150)(2875 4150);
|
|
FORCEPROP 2 LAST SIG_NAME SCALER<1..3>
|
|
J 0
|
|
(2565 4185);
|
|
DISPLAY 1.021277 (2565 4185);
|
|
PAINT ORANGE (2565 4185);
|
|
WIRE 16 -1 (2375 2300)(2825 2300);
|
|
FORCEPROP 2 LAST SIG_NAME DGT_N
|
|
J 0
|
|
(2465 2310);
|
|
DISPLAY 1.021277 (2465 2310);
|
|
PAINT ORANGE (2465 2310);
|
|
WIRE 16 -1 (2375 2375)(2825 2375);
|
|
FORCEPROP 2 LAST SIG_NAME DGT_P
|
|
J 0
|
|
(2490 2385);
|
|
DISPLAY 1.021277 (2490 2385);
|
|
PAINT ORANGE (2490 2385);
|
|
WIRE 16 -1 (950 1050)(400 1050);
|
|
FORCEPROP 2 LAST SIG_NAME EXT_PED_IN
|
|
J 0
|
|
(440 1085);
|
|
DISPLAY 1.021277 (440 1085);
|
|
PAINT ORANGE (440 1085);
|
|
WIRE 16 -1 (-1350 1000)(-1675 1000);
|
|
WIRE 16 -1 (1375 1875)(1000 1875);
|
|
FORCEPROP 2 LAST SIG_NAME MTCD_LO*
|
|
J 0
|
|
(1015 1910);
|
|
DISPLAY 1.021277 (1015 1910);
|
|
PAINT ORANGE (1015 1910);
|
|
WIRE 16 -1 (-3900 4700)(-3550 4700);
|
|
WIRE 16 -1 (-3900 5000)(-3900 4700);
|
|
WIRE 16 -1 (2775 5000)(-3900 5000);
|
|
WIRE 16 -1 (2775 4550)(2775 5000);
|
|
WIRE 16 -1 (2500 4550)(2775 4550);
|
|
WIRE 16 -1 (1375 2025)(800 2025);
|
|
WIRE 16 -1 (800 1700)(800 2025);
|
|
WIRE 16 -1 (3550 1700)(800 1700);
|
|
WIRE 16 -1 (3550 4450)(3550 1700);
|
|
WIRE 16 -1 (2500 4450)(3550 4450);
|
|
WIRE 16 -1 (2375 2075)(2825 2075);
|
|
FORCEPROP 2 LAST SIG_NAME LO_STAR_OUT_N
|
|
J 0
|
|
(2415 2085);
|
|
DISPLAY 1.021277 (2415 2085);
|
|
PAINT ORANGE (2415 2085);
|
|
WIRE 16 -1 (2825 2200)(2375 2200);
|
|
FORCEPROP 2 LAST SIG_NAME LO_STAR_OUT_P
|
|
J 0
|
|
(2415 2235);
|
|
DISPLAY 1.021277 (2415 2235);
|
|
PAINT ORANGE (2415 2235);
|
|
WIRE 17 -1 (2550 2925)(3150 2925);
|
|
FORCEPROP 2 LAST SIG_NAME CAEN_OUT_ANAL<0..7>
|
|
J 0
|
|
(2590 2935);
|
|
DISPLAY 1.021277 (2590 2935);
|
|
PAINT ORANGE (2590 2935);
|
|
WIRE 16 -1 (2550 3150)(3175 3150);
|
|
FORCEPROP 2 LAST SIG_NAME GT_TTL_OUT
|
|
J 0
|
|
(2590 3160);
|
|
DISPLAY 1.021277 (2590 3160);
|
|
PAINT ORANGE (2590 3160);
|
|
WIRE 16 -1 (350 2375)(350 2225);
|
|
FORCEPROP 2 LAST SIG_NAME VCC\G
|
|
R 1
|
|
J 0
|
|
(340 2210);
|
|
DISPLAY 1.021277 (340 2210);
|
|
PAINT ORANGE (340 2210);
|
|
WIRE 16 -1 (450 2375)(450 2225);
|
|
FORCEPROP 2 LAST SIG_NAME VCC\G
|
|
R 1
|
|
J 0
|
|
(440 2210);
|
|
DISPLAY 1.021277 (440 2210);
|
|
PAINT ORANGE (440 2210);
|
|
WIRE 16 -1 (-3550 4300)(-4125 4300);
|
|
FORCEPROP 2 LAST SIG_NAME TUB_CLK_IN_P
|
|
J 0
|
|
(-4110 4310);
|
|
DISPLAY 0.808511 (-4110 4310);
|
|
PAINT ORANGE (-4110 4310);
|
|
WIRE 16 -1 (-4125 4250)(-3550 4250);
|
|
FORCEPROP 2 LAST SIG_NAME TUB_CLK_IN_N
|
|
J 0
|
|
(-4110 4260);
|
|
DISPLAY 0.808511 (-4110 4260);
|
|
PAINT ORANGE (-4110 4260);
|
|
WIRE 16 -1 (-1725 2775)(-2150 2775);
|
|
FORCEPROP 2 LAST SIG_NAME LVDS_TO_ECL_OUT
|
|
J 0
|
|
(-2135 2810);
|
|
DISPLAY 1.021277 (-2135 2810);
|
|
PAINT ORANGE (-2135 2810);
|
|
WIRE 16 -1 (-2150 2500)(-1725 2500);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_TTL_OUT
|
|
J 0
|
|
(-2135 2510);
|
|
DISPLAY 1.021277 (-2135 2510);
|
|
PAINT ORANGE (-2135 2510);
|
|
WIRE 16 -1 (-2150 2425)(-1725 2425);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_LVDS_OUT_P
|
|
J 0
|
|
(-2135 2435);
|
|
DISPLAY 1.021277 (-2135 2435);
|
|
PAINT ORANGE (-2135 2435);
|
|
WIRE 16 -1 (-2150 2275)(-1725 2275);
|
|
FORCEPROP 2 LAST SIG_NAME ECL_TO_NIM_OUT
|
|
J 0
|
|
(-2135 2310);
|
|
DISPLAY 1.021277 (-2135 2310);
|
|
PAINT ORANGE (-2135 2310);
|
|
WIRE 16 -1 (-3850 4500)(-3550 4500);
|
|
WIRE 16 -1 (-3850 4975)(-3850 4500);
|
|
WIRE 16 -1 (625 2550)(650 2550);
|
|
WIRE 16 -1 (650 4975)(650 2550);
|
|
FORCEPROP 2 LAST SIG_NAME LE_CLKS
|
|
J 0
|
|
(665 4860);
|
|
DISPLAY 1.021277 (665 4860);
|
|
PAINT ORANGE (665 4860);
|
|
WIRE 16 -1 (-3850 4975)(650 4975);
|
|
WIRE 16 -1 (-1700 3225)(-2150 3225);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_OUT_N
|
|
J 0
|
|
(-2135 3260);
|
|
DISPLAY 1.021277 (-2135 3260);
|
|
PAINT ORANGE (-2135 3260);
|
|
WIRE 16 -1 (-1700 3325)(-2150 3325);
|
|
FORCEPROP 2 LAST SIG_NAME RIBBON_PULSE_OUT_P
|
|
J 0
|
|
(-2160 3335);
|
|
DISPLAY 1.021277 (-2160 3335);
|
|
PAINT ORANGE (-2160 3335);
|
|
WIRE 16 -1 (-2150 3400)(-1700 3400);
|
|
FORCEPROP 2 LAST SIG_NAME GENERIC_DELAY_OUT
|
|
J 0
|
|
(-2160 3410);
|
|
DISPLAY 1.021277 (-2160 3410);
|
|
PAINT ORANGE (-2160 3410);
|
|
WIRE 16 -1 (-1700 3475)(-2150 3475);
|
|
FORCEPROP 2 LAST SIG_NAME GENERIC_PULSE_OUT
|
|
J 0
|
|
(-2160 3485);
|
|
DISPLAY 1.021277 (-2160 3485);
|
|
PAINT ORANGE (-2160 3485);
|
|
WIRE 16 -1 (-2150 3125)(-1700 3125);
|
|
FORCEPROP 2 LAST SIG_NAME PULSE_INV_OUT
|
|
J 0
|
|
(-2135 3160);
|
|
DISPLAY 1.021277 (-2135 3160);
|
|
PAINT ORANGE (-2135 3160);
|
|
WIRE 16 -1 (-2150 2950)(-1725 2950);
|
|
FORCEPROP 2 LAST SIG_NAME TTL_TO_ECL_OUT
|
|
J 0
|
|
(-2160 2960);
|
|
DISPLAY 1.021277 (-2160 2960);
|
|
PAINT ORANGE (-2160 2960);
|
|
WIRE 16 -1 (-2150 2600)(-1725 2600);
|
|
FORCEPROP 2 LAST SIG_NAME NIM_TO_ECL_OUT
|
|
J 0
|
|
(-2135 2635);
|
|
DISPLAY 1.021277 (-2135 2635);
|
|
PAINT ORANGE (-2135 2635);
|
|
WIRE 16 -1 (700 2600)(625 2600);
|
|
WIRE 16 -1 (700 1525)(700 2600);
|
|
WIRE 16 -1 (-3525 3175)(-3675 3175);
|
|
WIRE 16 -1 (-3675 3175)(-3675 1900);
|
|
WIRE 16 -1 (-3675 1900)(-1825 1900);
|
|
WIRE 16 -1 (-1825 1525)(700 1525);
|
|
FORCEPROP 2 LAST SIG_NAME LE_GEN_UTILS
|
|
J 0
|
|
(-910 1560);
|
|
DISPLAY 1.021277 (-910 1560);
|
|
PAINT ORANGE (-910 1560);
|
|
WIRE 16 -1 (-1825 1900)(-1825 1525);
|
|
WIRE 16 -1 (-1850 1450)(-1850 775);
|
|
WIRE 16 -1 (-1850 775)(-1350 775);
|
|
WIRE 16 -1 (725 1450)(-1850 1450);
|
|
FORCEPROP 2 LAST SIG_NAME LE_MTCA_MIMIC
|
|
J 0
|
|
(-960 1410);
|
|
DISPLAY 1.021277 (-960 1410);
|
|
PAINT ORANGE (-960 1410);
|
|
WIRE 16 -1 (725 2700)(625 2700);
|
|
WIRE 16 -1 (725 1450)(725 2700);
|
|
WIRE 16 -1 (-1975 1175)(-1975 325);
|
|
WIRE 16 -1 (-1975 325)(-1350 325);
|
|
WIRE 16 -1 (875 1175)(-1975 1175);
|
|
WIRE 16 -1 (875 1725)(875 1175);
|
|
WIRE 16 -1 (875 1175)(950 1175);
|
|
WIRE 16 -1 (3325 1725)(875 1725);
|
|
WIRE 16 -1 (3325 3100)(3325 1725);
|
|
WIRE 16 -1 (2550 3100)(3325 3100);
|
|
WIRE 16 -1 (1850 1200)(2375 1200);
|
|
FORCEPROP 2 LAST SIG_NAME EXT_PED_OUT
|
|
J 0
|
|
(1915 1235);
|
|
DISPLAY 1.021277 (1915 1235);
|
|
PAINT ORANGE (1915 1235);
|
|
WIRE 16 -1 (-1650 250)(-1350 250);
|
|
WIRE 16 -1 (-1650 125)(-1650 250);
|
|
WIRE 16 -1 (500 125)(-1650 125);
|
|
WIRE 16 -1 (500 725)(500 125);
|
|
WIRE 16 -1 (2650 725)(500 725);
|
|
WIRE 16 -1 (2650 1975)(2650 725);
|
|
WIRE 16 -1 (2375 1975)(2650 1975);
|
|
WIRE 16 -1 (2500 4350)(3525 4350);
|
|
WIRE 16 -1 (3525 4350)(3525 1650);
|
|
WIRE 16 -1 (900 1650)(900 1300);
|
|
WIRE 16 -1 (900 1300)(950 1300);
|
|
WIRE 16 -1 (3525 1650)(900 1650);
|
|
WIRE 16 -1 (-1675 400)(-1350 400);
|
|
WIRE 16 -1 (-1675 75)(-1675 400);
|
|
WIRE 16 -1 (525 75)(-1675 75);
|
|
WIRE 16 -1 (525 700)(525 75);
|
|
WIRE 16 -1 (2675 700)(525 700);
|
|
WIRE 16 -1 (2675 1875)(2675 700);
|
|
WIRE 16 -1 (2375 1875)(2675 1875);
|
|
WIRE 16 -1 (-1200 1725)(-1350 1725);
|
|
WIRE 16 -1 (-1350 1725)(-1350 1400);
|
|
WIRE 16 -1 (-1350 1400)(800 1400);
|
|
WIRE 16 -1 (800 1400)(800 1625);
|
|
WIRE 16 -1 (800 1625)(2700 1625);
|
|
WIRE 16 -1 (2700 1625)(2700 1100);
|
|
WIRE 16 -1 (2700 1100)(2725 1100);
|
|
WIRE 16 -1 (200 2175)(525 2175);
|
|
WIRE 16 -1 (525 2375)(525 2175);
|
|
WIRE 16 -1 (-1200 3475)(-1450 3475);
|
|
WIRE 16 -1 (-1450 3475)(-1450 3900);
|
|
WIRE 16 -1 (-1450 3900)(-1875 3900);
|
|
WIRE 16 -1 (-1875 3900)(-1875 3975);
|
|
WIRE 16 -1 (-1875 3975)(-3675 3975);
|
|
WIRE 16 -1 (-3675 4200)(-3550 4200);
|
|
WIRE 16 -1 (-3675 3975)(-3675 4200);
|
|
WIRE 16 -1 (-1625 2100)(-1200 2100);
|
|
FORCEPROP 2 LAST SIG_NAME TUBII_RT_OUT
|
|
J 0
|
|
(-1685 2110);
|
|
DISPLAY 0.808511 (-1685 2110);
|
|
PAINT ORANGE (-1685 2110);
|
|
WIRE 16 -1 (-2050 2000)(-1200 2000);
|
|
WIRE 16 -1 (-2050 1200)(-2050 2000);
|
|
WIRE 16 -1 (-2050 1200)(-2175 1200);
|
|
WIRE 16 -1 (-2175 4425)(-2600 4425);
|
|
WIRE 16 -1 (-2175 3600)(-2175 4425);
|
|
WIRE 16 -1 (-1200 3600)(-2175 3600);
|
|
WIRE 16 -1 (300 4150)(1350 4150);
|
|
WIRE 16 -1 (300 3650)(300 4150);
|
|
WIRE 16 -1 (200 3650)(300 3650);
|
|
WIRE 16 -1 (1375 3900)(1375 3750);
|
|
WIRE 16 -1 (1375 3750)(200 3750);
|
|
WIRE 16 -1 (2675 3900)(1375 3900);
|
|
WIRE 16 -1 (2675 4025)(2675 3900);
|
|
WIRE 16 -1 (2500 4025)(2675 4025);
|
|
WIRE 16 -1 (225 4250)(1350 4250);
|
|
WIRE 16 -1 (225 3850)(225 4250);
|
|
WIRE 16 -1 (200 3850)(225 3850);
|
|
WIRE 16 -1 (-2000 1925)(-2000 350);
|
|
WIRE 16 -1 (-2000 350)(-2700 350);
|
|
FORCEPROP 2 LAST SIG_NAME SPKR
|
|
J 0
|
|
(-2610 385);
|
|
DISPLAY 1.021277 (-2610 385);
|
|
PAINT ORANGE (-2610 385);
|
|
WIRE 16 -1 (-1200 1925)(-2000 1925);
|
|
WIRE 16 -1 (250 2600)(275 2600);
|
|
WIRE 16 -1 (250 2575)(250 2600);
|
|
WIRE 16 -1 (200 2575)(250 2575);
|
|
WIRE 16 -1 (275 2700)(200 2700);
|
|
WIRE 16 -1 (275 2800)(200 2800);
|
|
WIRE 16 -1 (-1200 3850)(-1750 3850);
|
|
WIRE 16 -1 (-1200 3800)(-3800 3800);
|
|
WIRE 16 -1 (-3800 3375)(-3800 3800);
|
|
WIRE 16 -1 (-3525 3375)(-3800 3375);
|
|
WIRE 16 -1 (-3775 3450)(-3525 3450);
|
|
WIRE 16 -1 (-3775 3725)(-3775 3450);
|
|
WIRE 16 -1 (-3775 3725)(-1200 3725);
|
|
WIRE 16 -1 (-3725 4575)(-3550 4575);
|
|
WIRE 16 -1 (-3725 3300)(-3725 4575);
|
|
WIRE 16 -1 (-3525 3300)(-3725 3300);
|
|
WIRE 16 -1 (-3725 3300)(-3725 1850);
|
|
WIRE 16 -1 (-1900 1850)(-3725 1850);
|
|
WIRE 16 -1 (-1900 1500)(-1900 1850);
|
|
WIRE 16 -1 (-1900 1500)(-1900 650);
|
|
WIRE 16 -1 (-1900 650)(-1350 650);
|
|
WIRE 16 -1 (1350 4600)(750 4600);
|
|
WIRE 16 -1 (750 4600)(750 2975);
|
|
WIRE 16 -1 (-1900 1500)(750 1500);
|
|
WIRE 16 -1 (750 2100)(750 1500);
|
|
WIRE 16 -1 (1450 2975)(750 2975);
|
|
WIRE 16 -1 (750 2175)(750 2975);
|
|
WIRE 16 -1 (1375 2175)(750 2175);
|
|
WIRE 16 -1 (750 2100)(750 2175);
|
|
WIRE 16 -1 (750 2100)(200 2100);
|
|
FORCEPROP 2 LAST SIG_NAME SR_DATA
|
|
J 0
|
|
(265 2110);
|
|
DISPLAY 1.021277 (265 2110);
|
|
PAINT ORANGE (265 2110);
|
|
WIRE 16 -1 (-3700 4450)(-3550 4450);
|
|
WIRE 16 -1 (-3700 3225)(-3700 4450);
|
|
WIRE 16 -1 (-3525 3225)(-3700 3225);
|
|
WIRE 16 -1 (-3700 1875)(-3700 3225);
|
|
WIRE 16 -1 (-1875 1875)(-3700 1875);
|
|
WIRE 16 -1 (775 4475)(1350 4475);
|
|
WIRE 16 -1 (775 4475)(775 2925);
|
|
WIRE 16 -1 (-1875 1475)(-1875 1875);
|
|
WIRE 16 -1 (-1875 1475)(-1875 700);
|
|
WIRE 16 -1 (-1875 700)(-1350 700);
|
|
WIRE 16 -1 (775 1475)(-1875 1475);
|
|
WIRE 16 -1 (775 2925)(1450 2925);
|
|
WIRE 16 -1 (775 2275)(775 2925);
|
|
WIRE 16 -1 (775 2275)(1375 2275);
|
|
WIRE 16 -1 (775 2000)(775 2275);
|
|
WIRE 16 -1 (775 2000)(775 1475);
|
|
WIRE 16 -1 (200 2000)(775 2000);
|
|
FORCEPROP 2 LAST SIG_NAME SR_CLK
|
|
J 0
|
|
(240 2010);
|
|
DISPLAY 1.021277 (240 2010);
|
|
PAINT ORANGE (240 2010);
|
|
WIRE 16 -1 (1325 2800)(1325 2850);
|
|
WIRE 16 -1 (1325 2850)(200 2850);
|
|
WIRE 16 -1 (1450 2800)(1325 2800);
|
|
WIRE 16 -1 (-1925 1825)(-1925 575);
|
|
WIRE 16 -1 (-1925 575)(-1350 575);
|
|
WIRE 16 -1 (-1200 1825)(-1925 1825);
|
|
WIRE 16 -1 (-3750 4650)(-3550 4650);
|
|
WIRE 16 -1 (-3750 3650)(-3750 4650);
|
|
WIRE 16 -1 (-1200 3650)(-3750 3650);
|
|
WIRE 16 -1 (350 4275)(75 4275);
|
|
WIRE 16 -1 (350 3475)(350 4275);
|
|
WIRE 16 -1 (200 3475)(350 3475);
|
|
WIRE 16 -1 (400 4175)(400 3375);
|
|
WIRE 16 -1 (400 3375)(200 3375);
|
|
WIRE 16 -1 (400 4175)(75 4175);
|
|
WIRE 16 -1 (200 3100)(1225 3100);
|
|
WIRE 16 -1 (1225 2700)(1225 3100);
|
|
WIRE 16 -1 (2850 2700)(1225 2700);
|
|
WIRE 16 -1 (2850 2775)(2850 2700);
|
|
WIRE 16 -1 (2550 2775)(2850 2775);
|
|
WIRE 16 -1 (1200 2675)(1200 3050);
|
|
WIRE 16 -1 (1200 3050)(200 3050);
|
|
WIRE 16 -1 (2925 2675)(1200 2675);
|
|
WIRE 16 -1 (2925 2850)(2925 2675);
|
|
WIRE 16 -1 (2550 2850)(2925 2850);
|
|
WIRE 16 -1 (1175 2650)(1175 3000);
|
|
WIRE 16 -1 (1175 3000)(200 3000);
|
|
WIRE 16 -1 (1175 2650)(1175 2375);
|
|
WIRE 16 -1 (1175 2375)(1375 2375);
|
|
WIRE 16 -1 (3475 2650)(1175 2650);
|
|
WIRE 16 -1 (3475 3200)(3475 2650);
|
|
WIRE 16 -1 (2550 3200)(3475 3200);
|
|
WIRE 17 -1 (525 1875)(200 1875);
|
|
FORCEPROP 2 LAST SIG_NAME SCALER<4..6>
|
|
J 0
|
|
(215 1910);
|
|
DISPLAY 1.021277 (215 1910);
|
|
PAINT ORANGE (215 1910);
|
|
WIRE 16 -1 (-1400 3925)(-1400 3200);
|
|
WIRE 16 -1 (-1400 3200)(-1200 3200);
|
|
WIRE 16 -1 (-1625 3925)(-1400 3925);
|
|
WIRE 16 -1 (-1625 4700)(-1625 3925);
|
|
WIRE 16 -1 (-1400 4700)(-1625 4700);
|
|
WIRE 16 -1 (-1200 3275)(-1375 3275);
|
|
WIRE 16 -1 (-1375 3275)(-1375 3950);
|
|
WIRE 16 -1 (-1375 3950)(-1600 3950);
|
|
WIRE 16 -1 (-1600 4775)(-1400 4775);
|
|
WIRE 16 -1 (-1600 3950)(-1600 4775);
|
|
WIRE 16 -1 (-1350 3975)(-1350 3350);
|
|
WIRE 16 -1 (-1350 3350)(-1200 3350);
|
|
WIRE 16 -1 (-1525 3975)(-1350 3975);
|
|
WIRE 16 -1 (-1525 4200)(-1525 3975);
|
|
WIRE 16 -1 (-1400 4200)(-1525 4200);
|
|
WIRE 16 -1 (-1325 3425)(-1325 4000);
|
|
WIRE 16 -1 (-1325 3425)(-1200 3425);
|
|
WIRE 16 -1 (-1325 4000)(-1475 4000);
|
|
WIRE 16 -1 (-1475 4300)(-1400 4300);
|
|
WIRE 16 -1 (-1475 4000)(-1475 4300);
|
|
WIRE 16 -1 (-2150 4325)(-2150 3525);
|
|
WIRE 16 -1 (-2150 3525)(-1200 3525);
|
|
WIRE 16 -1 (-2600 4325)(-2150 4325);
|
|
WIRE 16 -1 (575 1800)(200 1800);
|
|
WIRE 16 -1 (575 1800)(575 925);
|
|
WIRE 16 -1 (0 925)(575 925);
|
|
WIRE 16 -1 (525 1725)(525 825);
|
|
WIRE 16 -1 (525 825)(0 825);
|
|
WIRE 16 -1 (200 1725)(525 1725);
|
|
WIRE 16 -1 (-1200 2200)(-1950 2200);
|
|
FORCEPROP 2 LAST SIG_NAME UNNUSED_MZ<0..15>
|
|
J 0
|
|
(-1910 2210);
|
|
DISPLAY 0.808511 (-1910 2210);
|
|
PAINT ORANGE (-1910 2210);
|
|
DOT 1 (-3700 3225);
|
|
DOT 1 (-3725 3300);
|
|
DOT 1 (1175 2650);
|
|
DOT 1 (-1900 1500);
|
|
DOT 1 (750 2175);
|
|
DOT 1 (775 2275);
|
|
DOT 1 (775 2000);
|
|
DOT 1 (750 2100);
|
|
DOT 1 (-1875 1475);
|
|
DOT 1 (875 1175);
|
|
DOT 1 (750 2975);
|
|
DOT 1 (775 2925);
|
|
FORCENOTE
|
|
14
|
|
(-775 675) 0;
|
|
DISPLAY LEFT (-775 675);
|
|
DISPLAY 1.021277 (-775 675);
|
|
PAINT PURPLE (-775 675);
|
|
FORCENOTE
|
|
13
|
|
(1800 2350) 0;
|
|
DISPLAY LEFT (1800 2350);
|
|
DISPLAY 1.021277 (1800 2350);
|
|
PAINT PURPLE (1800 2350);
|
|
FORCENOTE
|
|
12
|
|
(-700 4725) 0;
|
|
DISPLAY LEFT (-700 4725);
|
|
DISPLAY 1.021277 (-700 4725);
|
|
PAINT PURPLE (-700 4725);
|
|
FORCENOTE
|
|
11
|
|
(1875 3375) 0;
|
|
DISPLAY LEFT (1875 3375);
|
|
DISPLAY 1.021277 (1875 3375);
|
|
PAINT PURPLE (1875 3375);
|
|
FORCENOTE
|
|
10
|
|
(1400 1375) 0;
|
|
DISPLAY LEFT (1400 1375);
|
|
DISPLAY 1.021277 (1400 1375);
|
|
PAINT PURPLE (1400 1375);
|
|
FORCENOTE
|
|
9
|
|
(3175 975) 0;
|
|
DISPLAY LEFT (3175 975);
|
|
DISPLAY 1.021277 (3175 975);
|
|
PAINT PURPLE (3175 975);
|
|
FORCENOTE
|
|
8
|
|
(-2850 3050) 0;
|
|
DISPLAY LEFT (-2850 3050);
|
|
DISPLAY 1.021277 (-2850 3050);
|
|
PAINT PURPLE (-2850 3050);
|
|
FORCENOTE
|
|
6
|
|
(-3900 450) 0;
|
|
DISPLAY LEFT (-3900 450);
|
|
DISPLAY 1.021277 (-3900 450);
|
|
PAINT PURPLE (-3900 450);
|
|
FORCENOTE
|
|
5
|
|
(-3125 350) 0;
|
|
DISPLAY LEFT (-3125 350);
|
|
DISPLAY 1.021277 (-3125 350);
|
|
PAINT PURPLE (-3125 350);
|
|
FORCENOTE
|
|
4
|
|
(1825 4450) 0;
|
|
DISPLAY LEFT (1825 4450);
|
|
DISPLAY 1.021277 (1825 4450);
|
|
PAINT PURPLE (1825 4450);
|
|
FORCENOTE
|
|
3
|
|
(-575 2875) 0;
|
|
DISPLAY LEFT (-575 2875);
|
|
DISPLAY 1.021277 (-575 2875);
|
|
PAINT PURPLE (-575 2875);
|
|
FORCENOTE
|
|
2
|
|
(3075 100) 0;
|
|
DISPLAY LEFT (3075 100);
|
|
DISPLAY 1.021277 (3075 100);
|
|
PAINT PURPLE (3075 100);
|
|
FORCENOTE
|
|
15
|
|
(-2650 1400) 0;
|
|
DISPLAY LEFT (-2650 1400);
|
|
DISPLAY 1.021277 (-2650 1400);
|
|
PAINT PURPLE (-2650 1400);
|
|
FORCENOTE
|
|
7
|
|
(-3100 4525) 0;
|
|
DISPLAY LEFT (-3100 4525);
|
|
DISPLAY 1.021277 (-3100 4525);
|
|
PAINT PURPLE (-3100 4525);
|
|
QUIT
|