10 lines
201 B
VHDL
10 lines
201 B
VHDL
-- generated by newgenasym Sun Mar 01 03:06:01 2015
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity tubii_spkr is
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port (
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SPKR_SIG: IN STD_LOGIC);
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end tubii_spkr;
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