Tubii_Tk2/worklib/vref_gen/entity/verilog.v
2015-03-25 11:38:44 -04:00

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151 B
Verilog

// generated by newgenasym Tue Mar 24 13:12:45 2015
module vref_gen (vref5m);
output vref5m;
initial
begin
end
endmodule