10 lines
197 B
VHDL
10 lines
197 B
VHDL
-- generated by newgenasym Tue Mar 24 13:12:45 2015
|
|
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use work.all;
|
|
entity vref_gen is
|
|
port (
|
|
VREF5M: OUT STD_LOGIC);
|
|
end vref_gen;
|