bac-hardware/bacbus/bacBus-v4r1-pinout.csv

1	bacBus Pin Number	Pin Name	Type	Direction	Voltage Domain	Max Voltage	Bus Scope	Driver Type	Default State	State Definition	Max Current	Power Sequencing	Description	Notes
2	1	CAN_1_H	Differential Signal	Bidirectional	CAN PHY	-27 to +42 V	Per bus						Primary CAN bus differential high line	Termination provided at physical stack ends via solder jumpers. Note: Net name has _P suffix so it gets recognized as part of a differential pair by KiCad. Voltage transient (ISO7637-2): −150..+100 V. Vdiff abs max −5..+18 V.
3	2	CAN_1_L	Differential Signal	Bidirectional	CAN PHY	-27 to +42 V	Per bus						Primary CAN bus differential low line	Termination provided at physical stack ends via solder jumpers. Note: Net name has _N suffix so it gets recognized as part of a differential pair by KiCad. Voltage transient (ISO7637-2): −150..+100 V. Vdiff abs max −5..+18 V.
4	3	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
5	4	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
6	5	CAN_2_H	Differential Signal	Bidirectional	CAN PHY	-27 to +42 V	Per bus						Secondary redundant CAN bus high line	Used for automatic failover
7	6	CAN_2_L	Differential Signal	Bidirectional	CAN PHY	-27 to +42 V	Per bus						Secondary redundant CAN bus low line	Used for automatic failover
8	7	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
9	8	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
10	9	EPS_OK	Status Signal	Output by EPS	3.3V logic	3.6	Per bus	Push-pull	Low during BOOT	High: main rails stable, low: shutdown imminent		Enabled after BOOT, when not in LOW_POWER mode	Indicates EPS has enabled main rails and normal operation may begin	Nodes should delay high power functions until asserted
11	10	SYNC_PULSE	Timing Signal	Output by OBC	3.3V logic	3.6	Shared	Push-pull	Low	Rising edge is the system tick			System timing synchronization signal	Typical frequency 0.1-1 Hz
12	11	SAFE_MODE	Control Signal	Output by OBC	3.3V logic	3.6	Shared	Push-pull	Low	High: enter safe mode, low: system nominal		Enabled after BOOT or on anomaly	Forces nodes into predefined safe configuration. Nodes must shut down non-essential functions when asserted.
13	12	3V3_AUX_EN	Control Signal	Output by OBC	3.3V logic	3.6	Per bus	Push-pull	Low	High: nodes may use AUX power, low: do not use aux power		Enabled after BOOT when in LOW_POWER mode	Indicateds main rails are not available, but nodes that are configured to do so, may use AUX power
14	13	HDRM_EN	Inhibit Signal	Output by OBC	3.3V logic	3.6	Shared	Push-pull	Low	High: deploy hold-down and release mechanisms		30 minutes after entering BOOT (per CDS 14.1)	HDRMs for solar panels, antennas, booms may be released when asserted.
15	14	RF_EN	Inhibit Signal	Output by OBC	3.3V logic	3.6	Shared	Push-pull	Low	High: enable comms		45 minutes after entering BOOT (per CDS 14.1)	Enable signal for RF communication subsystem	Allows EPS to disable radios for safety or power management
16	15	PAYLOAD_EN	Control Signal	Output by OBC	3.3V logic	3.6	Per bus	Push-pull	Low	High: enable payload OPs		When system is in PAYLOAD mode	Enable line controlling payload power or activity	Allows staged activation of payload hardware. Note that there is one line is per bus, so A and B (or primary and secondary) payloads can be controlled independently.
17	16	GPIO_1	User-defined				Per bus							Available for user application
18	17	GPIO_2	User-defined				Per bus							Available for user application
19	18	GPIO_3	User-defined				Per bus							Available for user application
20	19	GPIO_4	User-defined				Per bus							Available for user application
21	20	GPIO_5	User-defined				Per bus							Available for user application
22	21	GPIO_6	User-defined				Per bus							Available for user application
23	22	GPIO_7	User-defined				Per bus							Available for user application
24	23	GPIO_8	User-defined				Per bus							Available for user application
25	24	3V3_MAIN	Power	Output	3.3V	3.6	Per bus				0.5A per pin, 6 pins per bacBus and Zm/Zp side = 0.5 * 6 * 2 * 2 = 12A system total	Enabled after EPS boot	Primary regulated 3.3V supply from EPS
26	25	3V3_MAIN	Power	Output	3.3V	3.6	Per bus				0.5A per pin, 6 pins per bacBus and Zm/Zp side = 0.5 * 6 * 2 * 2 = 12A system total	Enabled after EPS boot	Primary regulated 3.3V supply from EPS
27	26	3V3_MAIN	Power	Output	3.3V	3.6	Per bus				0.5A per pin, 6 pins per bacBus and Zm/Zp side = 0.5 * 6 * 2 * 2 = 12A system total	Enabled after EPS boot	Primary regulated 3.3V supply from EPS
28	27	3V3_MAIN	Power	Output	3.3V	3.6	Per bus				0.5A per pin, 6 pins per bacBus and Zm/Zp side = 0.5 * 6 * 2 * 2 = 12A system total	Enabled after EPS boot	Primary regulated 3.3V supply from EPS
29	28	3V3_MAIN	Power	Output	3.3V	3.6	Per bus				0.5A per pin, 6 pins per bacBus and Zm/Zp side = 0.5 * 6 * 2 * 2 = 12A system total	Enabled after EPS boot	Primary regulated 3.3V supply from EPS
30	29	3V3_MAIN	Power	Output	3.3V	3.6	Per bus				0.5A per pin, 6 pins per bacBus and Zm/Zp side = 0.5 * 6 * 2 * 2 = 12A system total	Enabled after EPS boot	Primary regulated 3.3V supply from EPS
31	30	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
32	31	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
33	32	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
34	33	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
35	34	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
36	35	3V3_AUX	Power	Output	3.3V	3.6	Shared				0.5A per pin, 2 pins per bacBus and Zm/Zp side = 0.5 * 2 * 2 * 2 = 4A system total	Enabled when RBF removed and deployment switches released	Always-on auxiliary rail. Used by EPS for bootstrapping and minimal system controllers.	Used by EPS and minimal system controllers, do not backfeed
37	36	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
38	37	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
39	38	VBAT	Power	Output	Battery bus	16.8	Shared				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled when RBF removed and deployment switches released	Raw battery voltage distributed across stack	Do not backfeed
40	39	VBAT	Power	Output	Battery bus	16.8	Shared				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled when RBF removed and deployment switches released	Raw battery voltage distributed across stack	Do not backfeed
41	40	VBAT	Power	Output	Battery bus	16.8	Shared				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled when RBF removed and deployment switches released	Raw battery voltage distributed across stack	Do not backfeed
42	41	VBAT	Power	Output	Battery bus	16.8	Shared				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled when RBF removed and deployment switches released	Raw battery voltage distributed across stack	Do not backfeed
43	42	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
44	43	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
45	44	RBF	Inhibit Signal	Input	VBAT	16.8	Shared	Open-drain with pull-up	Pull-up to VBAT (2x 100k = 50k)	Low: RBF feature applied, high: RBF feature removed			Remove Before Flight safety inhibit line	Held low to GND by safety pin prior to integration
46	45	DEPLOY_SW_1	Inhibit Signal	Input	VBAT	16.8	Shared	Open-drain with pull-up	Pull-up to +BAT (2x 100k = 50k)	Low: deployment switches closed (stowed), high: deployment switches open (released)			Deployment switch group 1: 1 to 4 rail-end switches in 4s, 2s2p or 4p configuration.
47	46	DEPLOY_SW_2	Inhibit Signal	Input	VBAT	16.8	Shared	Open-drain with pull-up	Pull-up to +BAT (2x 100k = 50k)	Low: deployment switches closed (stowed), high: deployment switches open (released)			Deployment switch group 2: 1 to 4 rail-end switches in 4s, 2s2p or 4p configuration.
48	47	RESERVED_1	Power or signal				Per bus						Reserved for future use	Do not use
49	48	RESERVED_2	Power or signal				Per bus						Reserved for future use	Do not use
50	49	RESERVED_3	Power or signal				Per bus						Reserved for future use	Do not use
51	50	GPIO_9	User-defined				Per bus							Available for user application
52	51	GPIO_10	User-defined				Per bus							Available for user application
53	52	GPIO_11	User-defined				Per bus							Available for user application
54	53	GPIO_12	User-defined				Per bus							Available for user application
55	54	GPIO_13	User-defined				Per bus							Available for user application
56	55	GPIO_14	User-defined				Per bus							Available for user application
57	56	GPIO_15	User-defined				Per bus							Available for user application
58	57	GPIO_16	User-defined				Per bus							Available for user application
59	58	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
60	59	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
61	60	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
62	61	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
63	62	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
64	63	GND	Power Return		GND	0	Shared					Always connected, battery pack load switches are high-side	System ground return	All boards must connect grounds internally
65	64	5V_MAIN	Power	Output	5V	5.5	Per bus				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled after EPS boot	Primary regulated 5V supply from EPS	Do not backfeed
66	65	5V_MAIN	Power	Output	5V	5.5	Per bus				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled after EPS boot	Primary regulated 5V supply from EPS	Do not backfeed
67	66	5V_MAIN	Power	Output	5V	5.5	Per bus				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled after EPS boot	Primary regulated 5V supply from EPS	Do not backfeed
68	67	5V_MAIN	Power	Output	5V	5.5	Per bus				0.5A per pin, 4 pins per bacBus and Zm/Zp side = 0.5 * 4 * 2 * 2 = 8A system total	Enabled after EPS boot	Primary regulated 5V supply from EPS	Do not backfeed