mirror of
https://github.com/oxidecomputer/hw-lpc55-carrier.git
synced 2024-11-22 09:04:40 +00:00
204 lines
8.7 KiB
Markdown
204 lines
8.7 KiB
Markdown
# Schematic Checklist
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## General
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* [x] CAD ERC 100% clean. If some errors are invalid due to toolchain quirks, each exception must be inspected and signed
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off as invalid.
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* [x] Verify pin numbers of all schematic symbols against datasheet or external interface specification document (if not yet board proven).
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* [x] Schematic symbol matches chosen component package
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* [x] Thermal pads are connected to correct power rail (may not always be ground)
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* [x] Debug interfaces are not power gated in sleep mode
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## Passive components
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* [x] Power/voltage/tolerance ratings specified as required
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* [x] Ceramic capacitors appropriately de-rated for C/V curve
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* [x] Polarized components specified in schematic if using electrolytic caps etc
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## Power supply
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## System power input
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* [x] Fusing and/or reverse voltage protection at system power inlet
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* [x] Check total input capacitance and add inrush limiter if needed
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## Regulators
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* [x] Under/overvoltage protection configured correctly if used
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* [x] Verify estimated power usage per rail against regulator rating
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* [x] Current-sense resistors on power rails after regulator output caps, not in switching loop
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* [x] Remote sense used on low voltage or high current rails
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* [x] Linear regulators and voltage reference ICs are stable with selected output cap ESR
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* [x] Confirm power rail sequencing against device datasheets
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## Decoupling
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* [x] Decoupling present for all ICs
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* [x] Decoupling meets/exceeds vendor recommendations if specified
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* [x] Bulk decoupling present at PSU
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## General
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* [x] All power inputs fed by correct voltage
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* [x] Check high-power discrete semiconductors and passives to confirm they can handle expected load
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* [x] Analog rails filtered/isolated from digital circuitry as needed
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## Signals
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## Digital
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* [X] Signals are correct logic level for input pin
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* [x] Pullups on all open-drain outputs
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* [x] Pulldowns on all PECL outputs
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* [x] Termination on all high-speed signals
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* [x] AC coupling caps on gigabit transceivers
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* [x] TX/RX paired correctly for UART, SPI, MGT, etc
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* [x] Differential pair polarity / pairing correct
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* [x] Active high/low enable signal polarity correct
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* [x] I/O banking rules met on FPGAs etc
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## Analog
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* [x] RC time constant for attenuators sane given ADC sampling frequency
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* [x] Verify frequency response of RF components across entire operating range. Don't assume a "1-100 MHz" amplifier has the
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same gain across the whole range.
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* [x] Verify polarity of op-amp feedback
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## Clocks
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* [x] All oscillators meet required jitter / frequency tolerance. Be extra cautious with MEMS oscillators as these tend to have higher jitter.
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* [x] Correct load caps provided for discrete crystals
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* [x] Crystals only used if IC has an integrated crystal driver
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* [x] Banking / clock capable input rules met for clocks going to FPGAs
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* [ ] Xilinx FPGAs: single ended clocks use _P half of differential pairs
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* [ ] If possible, create dummy design with all clocks and other key signals and verify it P&R's properly
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## Strap/init pins
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* [x] Pullup/pulldowns on all signals that need defined state at boot
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* [x] Strap pins connected to correct rail for desired state
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* [x] JTAG/ICSP connector provided for all programmable devices
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* [x] Config/boot flash provided for all FPGAs or MPUs without internal flash
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* [x] Reference resistors correct value and reference rail
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## External interface protection
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* [x] Power outputs (USB etc) current limited
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* [x] ESD protection on data lines going off board
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## Debugging / reworkability
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* [x] Use 0-ohm resistors vs direct hard-wiring for strap pins when possible
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* [x] Provide multiple ground clips/points for scope probes
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* [x] Dedicated ground in close proximity to analog test points
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* [x] Test points on all power rails
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* [x] Test points on interesting signals which may need probing for bringup/debug
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## Thermal
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* [x] Power estimates for all large / high power ICs
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* [x] Thermal calculations for all large / high power ICs
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* [x] Specify heatsinks as needed
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# PCB Checklist
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## General
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* [x] [Schematic review](schematic-checklist.md) complete and signed off, including pin swaps done during layout
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* [x] Layout DRC 100% clean
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## Decoupling
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* [ ] Decoupling caps as close to power pins as possible
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* [ ] Low inductance mounting used for decoupling (prefer ViP if available, otherwise "[]8" shaped side vias
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## DFM / yield enhancement
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* [x] All design rules within manufacturer's capability
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* [x] Minimize use of vias/traces that push fab limits
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* [x] Controlled impedance specified in fab notes if applicable
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* [x] Confirm impedance calculations include soldermask, or mask removed from RF traces
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* [x] Stackup verified with manufacturer and specified in fab notes
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* [x] Board finish specified in fab notes
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* [x] If panelizing, add panel location indicators for identifying location-specific reflow issues
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* [x] (recommended) Layer number markers specified to ensure correct assembly
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* [x] Fiducials present (on both sides of board) if targeting automated assembly
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* [x] Fiducial pattern asymmetric to detect rotated or flipped boards
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* [x] Soldermask/copper clearance on fiducials respected
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* [x] Panelization specified if required
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## Footprints
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* [x] Confirm components are available in the selected package
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* [x] Confirm components (especially connectors and power regulators) are capable of desired current in the selected package
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* [x] Verify schematic symbol matches the selected package
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* [x] Confirm pinout diagram is from top vs bottom of package
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* [x] (recommended) PCB printed 1:1 on paper and checked against physical parts
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* [x] 3D models obtained (if available) and checked against footprints
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* [x] Soldermask apertures on all SMT lands and PTH pads
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## Differential pairs
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* [x] Routed differentially
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* [x] Skew matched
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* [x] Correct clearance to non-coupled nets
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## High-speed signals
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* [x] Sufficient clearance to potential aggressors
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* [x] Length matched if required
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* [x] Minimize crossing reference plane splits/slots or changing layers, use caps/stitching vias if unavoidable
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* [x] Confirm fab can do copper to edge of PCB for edge launch connectors
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* [x] Double-check pad width on connectors and add plane cutouts if needed to minimize impedance discontinuities
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## Power
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* [x] Minimal slots in planes from via antipads
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* [x] Sufficient width for planes/traces for required current
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## Sensitive analog
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* [x] Guard ring / EMI cages provided if needed
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* [x] Physically separated from high current SMPS or other noise sources
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* [x] Consider microphone effect on MLCCs if near strong sound sources
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## Mechanical
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* [x] Confirm all connectors to other systems comply with the appropriate mechanical standard (connector orientation, key position, etc)
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* [x] LEDs, buttons, and other UI elements on outward-facing side of board
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* [x] Keep-outs around PCB perimeter, card guides, panelization mouse-bites, etc respected
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* [x] Stress-sensitive components (MLCC) sufficiently clear from V-score or mouse bite locations, and oriented to reduce
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bending stress
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* [x] Clearance around large ICs for heatsinks/fans if required
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* [x] Clearance around pluggable connectors for mating cable/connector
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* [x] Clearance around mounting holes for screws
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* [x] Plane keepouts and clearance provided for shielded connectors, magnetics, etc
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* [x] Confirm PCB dimensions and mounting hole size/placement against enclosure or card rack design
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* [x] Verify mounting hole connection/isolation
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* [x] Components not physically overlapping/colliding
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* [x] Clearance provided around solder-in test points for probe tips
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## Thermal
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* [x] Thermal reliefs used for plane connections (unless via is used for heatsinking)
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* [x] Solid connections used to planes if heatsinking
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* [x] Ensure thermal balance on SMT chip components to minimize risk of tombstoning
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## Solder paste
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* [x] No uncapped vias in pads (except low-power QFNs where some voiding is acceptable)
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* [x] QFN paste prints segmented
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* [x] Small pads 100% size, larger pads reduced to avoid excessive solder volume
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* [x] No paste apertures on card edge connectors or test points
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## Solder mask
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* [x] Confirm SMD vs NSMD pad geometry
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* [x] Adequate clearance around pads (typ. 50 um)
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## Silkscreen
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* [x] Text size within fab limits
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* [x] Text not overlapping drills or component pads
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* [x] Text removed entirely in, or moved outside of, high component/via density areas
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* [x] Traceability markings (rev, date, name, etc) provided
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* [x] Silkscreen box provided for writing/sticking serial number
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* [x] Text mirrored properly on bottom layer
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* [x] Test points labeled if space permits
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## CAM production
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* [ ] KiCAD specific: rerun DRC and zone fills before exporting CAM files to ensure proper results
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* [ ] Export gerber/drill files at the same time to ensure consistency
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* [ ] Visually verify final CAM files to ensure no obvious misalignments
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