AllSpiceMirrors/jellyfish-powersupply
0
Fork 0
mirror of https://gitlab.com/hyperglitch/jellyfish.git synced 2025-03-29 00:46:33 +00:00
Files Issues Releases Activity
19 Commits 1 Branch 0 Tags 55 MiB
main
Commit Graph

19 Commits

Author SHA1 Message Date
Igor Brkic
90fe822d7c add licenses 2025-03-09 01:00:16 +01:00
Igor Brkic
d3b89c87b1 add firmware code 2025-03-09 00:59:24 +01:00
Igor Brkic
f6628e778b add verilog files 2025-03-09 00:37:34 +01:00
Igor Brkic
b6287c72da add annotations for the changes to the schematic 2025-03-06 15:13:07 +01:00
Igor Brkic
63efd9a6b0 PCB done for first prototype, production files ready 2024-07-13 00:35:20 +02:00
Igor Brkic
b7ade1a23e routing done 2024-07-06 19:57:39 +02:00
Igor Brkic
21a3dedb0c routing done 90%, board layout defined 2024-06-22 18:39:47 +02:00
Igor Brkic
ce239e3af6 add fw+gw placeholders 2024-04-12 23:32:38 +02:00
Igor Brkic
3efa6c6a71 add nlnet info to readme 2024-04-12 23:31:37 +02:00
Igor Brkic
acc8a69ef6 add pdf schematic 2024-04-11 11:42:21 +02:00
Igor Brkic
dcf8914720 ina supply filtering, small changes 2024-04-11 11:40:47 +02:00
Igor Brkic
6a8b4dfa41 ignore temporary fab files 2024-04-11 11:39:50 +02:00
Igor Brkic
332ec4c8a5 production folder cleanup 2024-04-11 11:38:44 +02:00
Igor Brkic
a323325e5d add licensing info according to REUSE 2024-04-10 12:19:16 +02:00
Igor Brkic
e9e1c3984c remove backup files 2024-04-10 12:04:31 +02:00
Igor Brkic
2976d52776 full schematic first commit 2024-04-10 11:53:27 +02:00
Igor Brkic
69520646c1 add output stage simulation (LTSpice) 2023-11-06 15:17:36 +01:00
Igor Brkic
7964e0d7e1 license update 2023-11-06 15:15:33 +01:00
Igor Brkic
ce869259f3 initial testing revision of the output stage 2023-11-06 15:12:31 +01:00