* USB_A_Molex_67643_Horizontal
* Molex_67643, silk moved from under component, added pin1 designator
* USB_A_Molex_67643_Horizontal
moved silk from copper
better description
* Fix ublox_NEO footprint missing paste on VCC pad 23
Resolves#2204
* Modify silkscreen outline
The existing silkscreen outlines for ublox NEO, LEA and MAX parts had variable clearances of, in some cases, just 0.01mm to copper pads - modified to give 0.2mm clearance as per KLC guidelines.
Because [particularly on the MAX part] this makes pin 1 less clear, I have reduced the silkscreen around pin 1 to make it more readily identifiable. If there is a preferred approach e.g. additional silkscreen as per SOIC parts, I would be happy to modify accordingly.
* Update ublox NEO, MAX and LEA to IPC-7351C style roundrect pads
* Modified assembly layer to KLC preferred 1mm bevel
Modified assembly layer to KLC-preferred 1mm bevel instead of pin 1 marker
* Modify silkscreen to extend around pin 1 as agreed
Silkscreen outline now extends around pin 1 as per scripted SOIC footprints
* Fix a couple relay footprints
* Review fixes
- Correct one 30.22 fab line to horizontal
- Make 30.22 fab layer bevel exactly 1mm
- All fab lines now 0.1mm wide
- 30.22 silk lines now 0.11mm from fab lines and pin 1 silk mark 0.25mm from other silk lines
Co-authored-by: evanshultz <evanshultz@gmail.com>
* Fix hole sizes in 2.54 mm headers.
The holes were previously 0.8 mm diameter, which is too small to
accommodate a standard header. Normal header posts are 0.025" square
(0.635 mm), and so the diagonal (approx. 0.898 mm) will not fit into
a 0.8 mm hole. 1.0 mm is an appropriate size.
* Fix hole sizes in 2.54 mm headers (for Arduino Nano footprints).
The same modification made in the parent commit:
The holes were previously 0.8 mm diameter, which is too small to
accommodate a standard header. Normal header posts are 0.025" square
(0.635 mm), and so the diagonal (approx. 0.898 mm) will not fit into
a 0.8 mm hole. 1.0 mm is an appropriate size.
now applied to the Nano footprints.
* Restore PLCC-32 THT socket footprint
This footprint was removed in https://github.com/KiCad/kicad-footprints/pull/675 along with some incorrect footprints. This footprint seems to be correct.
* Fix courtyard size
* Fix courtyard again
* Add datasheet link to footprint description
* Create TE_5767171-1_2x19_P0.635mm_Vertical.kicad_mod
* Update TE_5767171-1_2x19_P0.635mm_Vertical.kicad_mod
* Fix F5.1 and F5.2
* Fix F6.2
* Add datasheet url
* Move silkscreen out of fab line
* Fix courtyard
* Fix courtyard to be same distance on both sides
Remove pin 1 marker on fab layer
* Center part as this is an smt component and the center is used for the plastic clip that the pick and place grabs on these kinds of connectors
Shift part dimensions to match drawings. A few things were off by a handful of mm
Shift courtyard to be 0.5mm from nearest features. It was too far away on the sides by a few tenths of a mm.
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Added Wuerth 614004143726 USB-A socket
* Added properties
* Fix position and line width
* Moved courtyard to correct grid
* Changes requested
* Shift pin 1 silk to be 0.2mm away from nearest pad
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Create RJ45_Wuerth_7499111446_Horizontal.kicad_mod
* Fix F7.2 and F9.3
* Fix F5.3
* Rotate part
* Fix silkscreen and courtyard
* Fix courtyard
* Expand pad size of holes to match other jacks
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Converter_DCDC_TRACO_THD_15-xxxxWIN_THT adjust rotation of pads to 0 by swapping size and size x values
* Converter_DCDC_TRACO_THD_15-xxxxWIN_THT fabrication, courtyard and silk fixes
* Adds Connector RJ11 Connfly DS1133-S4
* change pad size
* travis findings
* Review changes
* moves silk
* better gap silk fab
* Increase mounting hole size from 2.2 to 2.3mm to match recommended datasheet footprint. Move silk slightly away from mounting holes.
* Fix courtyard to go around the mounting holes.
* Change courtyard to arch around mounting holes
* Add Pin1 marker on fab layer
* Review fixes
rename to RJ14
add orientation to designator
move pin1 marker closer to silk
courtyard space to mounting holes
gap between silk and fab to zero
silk to close to mounting holes
* Fix 3D modle name
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Add RJ45-Molex vertical connector footprint
The Molex 85513 series is a surface-mount only (no mechanical via/holes)
RJ45 unshielded vertical plug. Product webpage at
https://www.molex.com/molex/products/part-detail/modular_jacks_plug/0855135013.
* fix build errors
Fix errors for https://travis-ci.org/github/KiCad/kicad-footprints/builds/664247247:
- change Ref** to REF**
- change line width in F.Fab
- move footprint by (-.3,0)mm
- add wrl model path
* decrease courtyard size to 0.5, increase silk distance
- the distance of the courtyard was previously calculated from the silk
layer, not the actual connector
- increased gap between element on silk and copper layer.
* Wrapping courtyard layer
- Wrapping courtyard in 0.5mm on 0.01mm grid around part dimensions of
connector (F5.3) and requested in https://github.com/KiCad/kicad-footprints/pull/2157#issuecomment-601609102
* ASMB-KTF0-0A306 Again
* Corrections
* Correction to ',' tag
* Add datasheet to part description
* Shift silk screen to be 0.2mm away from pads. Fix pad locations to match datasheet.
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Connector_BarrelJack: Add CLIFF FC681465S DC socket
* Connector_BarrelJack: Correct FC681465S pin numbering
* Connector_BarrelJack: Replace datasheet URL with a correct one
* Add pin 1 indicator to silk
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Create Molex_Pico-SPOX_87437-1443_1x14-P1.5mm_Vertical.kicad_mod
* Fix datasheet URL
* Fix SilkScreen position
* Fix pad spacing and fab line
* Fix courtyard
* Add pin 1 indicator
* Extended fab lines through part for better visibility of part outline
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Added footprint for CUI CMT-8504-100-SMT
* Added footprint for CUI CMT-8504-100-SMT.
Datasheet: CUI_CMT-8504-100-SMT
* Adjust courtyard and change 3D model from stp to wrl
* Fixed courtyard and 3D model name
* Added footprint for CUI CMT-8504-100-SMT
* Added footprint for CUI CMT-8504-100-SMT.
Datasheet: CUI_CMT-8504-100-SMT
* Adjust courtyard and change 3D model from stp to wrl
* Fixed courtyard and 3D model name
* Added polarity mark in silkscreen and datasheet link to description field
* Added footprint for CUI CMT-8504-100-SMT
* Added footprint for CUI CMT-8504-100-SMT.
Datasheet: CUI_CMT-8504-100-SMT
* Adjust courtyard and change 3D model from stp to wrl
* Fixed courtyard and 3D model name
* Added polarity mark in silkscreen and datasheet link to description field
* Remove '+' silkscreen mark inside component.
* added ESP32-S2 SoC Module
* fixed errors from check script
* Pads 40/41 in wrong order
* REF got changed to U1 (editing from pcbnew?)
* add reference to not existing as of yet 3d model
* fix EPAD size
* moved silk completely clear of Fab
* fix pad orientation along bottom edge
* fixed fab line length
* fixed courtyard spacing
* include url in description
* Adjust bottom silk alignment for consistency, move 0.2mm away from pads per KLC, add pin 1 indicator to silk and fab, add 5 pin silk markings to aid in debugging
Co-authored-by: Chris Morgan <chmorgan@gmail.com>
* Added Omron B3FS tactile switch series.
Datasheet: https://omronfs.omron.com/en_US/ecb/products/pdf/en-b3fs.pdf
* Added datasheet link to description field
* Added pin 1 location mark in silkscreen.
* Fixed courtyard to be 0.25mm away from the body
* Fixed silkscreen line thickness
