- Adds time and delay units
- Adds time domain tuning parameters entry and storage
- Adds pad-to-die delay property
- Adds time domain parameter interface for length / delay calculations
- Adds unit tracking for numerical constants through LIBEVAL
- Will need future work to truly propagate through binary expressions
- Adds time domain tuning to meander placers
- Adds time delay display to net inspector panel
- Modifies DRC to handle time domain constraints
The arc center is a pseudo coordinate which is calculated for drawing
purposes. This mid point is fixed unless the arc is modified which
should result in more reliable arc parity footprint library DRC testing.
Also change EDA_SHAPE::Compare() to use the arc mid point.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/15917
Support explicit jumper symbols, defined either by a
flag that all pins with the same number are connected,
or by explicit groups of jumpered pins
Fixes https://gitlab.com/kicad/code/kicad/-/issues/2558
When building a net tie, all elements in the footprint that belong to
the net tie can be arbitrarily close to one another. outside of the
footprint, connected items can be arbitrarily close to the tie element
but must respect the clearance values for elements that have nets
assigned to them
Fixes https://gitlab.com/kicad/code/kicad/-/issues/19933
(cherry picked from commit bff819edb0)
This is not only a useful place to hang regression tests,
but also allows to catch defects specific to loading or
saving footprints.
For example, it would catch:
Relates-To: https://gitlab.com/kicad/code/kicad/-/issues/19713
- Remove bespoke collide routine. We should never rewrite these instead
of using the geometry library
- Optimize check by creating unified geometry before colliding
- Make extra variable that we don't need but makes cherry-picks easier
(min/maxAnnularWidth)
Fixes https://gitlab.com/kicad/code/kicad/-/issues/19325
(cherry picked from commit a611c72c27)
Items that are part of net ties (pads and copper shapes that connect to
them) should allow connections from any net in the tie. This prevents
clearance errors from being generated for matched nets
Fixes https://gitlab.com/kicad/code/kicad/-/issues/14008
If two nets are joined by a global power pin but both have global labels
that override the net name, we still want them to be merged. This
checks for all net names in the drivers when looking for subgraph
merging candidates
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18092
There was a motion towards fill solid/none around
2020 (c.f. b31e97cfed),
but it was only for PCB_SHAPE.
Use yes/no universally (solid/none parsing the same way
as currently). In future if there are other fill modes
for these shapes, they can use the same pattern as ZONEs
do now: (fill yes) (hatch etc ....) or similar.
Relates-To: https://gitlab.com/kicad/code/kicad/-/issues/15232
When zone kisses happen from different polygons, we need to be careful
not to use the different polygons for ear comparisons or prev/next
pointers
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18654
- Moves functionality to FOOTPRINT class from BOARD_ITEM
- Renames DRC property from ComponentClass to Component_Class
- Adds DRC checks QA for A.Component_Class and a.hasComponentClass('x')
CHANGED: PCB file format now supports saving/loading complex padstacks
CHANGED: PTH pads are now rendered per copper layer in the copper color;
the PTH pad color is no longer used.
ADDED: support for importing complex pad stacks from Altium PCBs
Enforce padstack-aware access to pad properties across KiCad
Fixes https://gitlab.com/kicad/code/kicad/-/issues/8182
- Adds Component Class field to SCH_DIRECTIVE_LABEL
- Adds SCH_SYMBOLs to SCH_RULE_AREA item lists
- SCH_SYMBOLs resolve Component Class directives
- Netlist exporter / importer handles Component Class names
- Adds DRC expressions and functions
- Adds QA check for component class netlist export
F_Cu = 0
B_Cu = 2
Remaining internal copper layers are even and incrementing
Non-copper layers are odd and incrementing.
This means that we can no longer do things like:
for( PCB_LAYER_ID layer = F_Cu; layer <= B_Cu; ++layer)
Instead, we have the class LAYER_RANGE:
for( PCB_LAYER_ID layer : LAYER_RANGE( F_Cu, B_Cu) )
Similarly, gt/lt tests should not refer to the integer value of the
layer. We have functions such as IsCopperLayer to test whether a layer
is copper or not.
When using the connectivity RTree, the third dimension is layer, so we
provide B_Cu with the special INT_MAX value, ensuring that elements
between F_Cu and B_Cu will be identified. There is a new, special
function GetBoardLayer() for interfacing with CN_ITEMS
Similarly, PNS layers remain unchanged and sequential. A set of
interface functions is provided to map PNS layers to Board layers and
back. This allows the PNS_LAYER_RANGE to function as expected
Enables DRC to calculate skew based on new arguments to skew
constraint DRC clauses:
Using (group_matched): calculate skew across all matching nets
Using (within_diff_pairs): calculate skew within every diff pair
found within the matching nets
Additionally fixes DRC skew calculation to calculate skew relative
to the longest net in the skew check set (in line with PNS meander
placer calculations).
