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Starting work on a proper README file..

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# Contributing to Parallella
If you are interested in contributing to Parallella, here are some instructions to get you started. Thank you!
### Coding Guidelines
* Language: Verilog (sorry, no VHDL)
* Style: A coding manual to be published soon (stay tuned)
### Board Design
* KiCad strongly encouraged
* Otherwise, we are glad to serve as a repo for any Parallella related hardware design project (Eagle, Mentor, Cadence, etc).
### Contribution advice
* Keep changes small (especially if you are a new contributor)
* You are responsible for not breaking something with your PR
* Include examples/test code for pull request
### Contribution Conventions
* If it's a bug fix branch, name it XXXX-something where XXXX is the number of
the issue.
* If it's a feature branch, create an enhancement issue to announce your
intentions, and name it XXXX-something where XXXX is the number of the issue.
* Pull requests descriptions should be as clear as possible and include a
reference to all the issues that they address.
* Commit messages must start with a capitalized and short summary (max. 50
chars) written in the imperative, followed by an optional, more detailed
explanatory text which is separated from the summary by an empty line.
* Code review comments may be added to your pull request. Discuss, then make
the suggested modifications and push additional commits to your feature branch. Be sure to post a comment after pushing. The new commits will show up in the
pull request automatically, but the reviewers will not be notified unless you
comment.
* Pull requests must be cleanly rebased ontop of master without multiple branches mixed into the PR.
* Before the pull request is merged, make sure that you squash your commits into
logical units of work using `git rebase -i` and `git push -f`. After every
commit the test suite should be passing. Include documentation changes in the
same commit so that a revert would remove all traces of the feature or fix.
### How to submit a pull request?
1. Modify the code
2. Run and pass the regression suite
3. Submit a pull request:
### How to file a bug report?
For standard issues like bugs and documentation errors please fill out an [issue ticket](https://github.com/parallella/parallella-hw/issues)
### How to submit a feature proposals?
0. Check the [Parallella forum](https://forums.parallella.org/) and [Issue Manager](https://github.com/parallella/parallella-hw/issues) for work in progress
1. Describe the problem the proposal solves
2. Provide a compelling use case
3. Post and discuss your proposal on the [Parallella forum](https://forums.parallella.org/)
4. Submit a pull request that modifies the documentation and adding new documentation as necessary
### Signoff Requirement
All major code contribution requires a sign-off. The sign-off is a simple line at the end of the explanation for the patch, which certifies that you wrote it or otherwise have the right to pass it on as an open-source patch. The rules are pretty simple: if you can certify the below (from
[developercertificate.org](http://developercertificate.org/)):
```
Developer Certificate of Origin
Version 1.1
Copyright (C) 2004, 2006 The Linux Foundation and its contributors.
660 York Street, Suite 102,
San Francisco, CA 94110 USA
Everyone is permitted to copy and distribute verbatim copies of this
license document, but changing it is not allowed.
Developer's Certificate of Origin 1.1
By making a contribution to this project, I certify that:
(a) The contribution was created in whole or in part by me and I
have the right to submit it under the open source license
indicated in the file; or
(b) The contribution is based upon previous work that, to the best
of my knowledge, is covered under an appropriate open source
license and I have the right under that license to submit that
work with modifications, whether created in whole or in part
by me, under the same open source license (unless I am
permitted to submit under a different license), as indicated
in the file; or
(c) The contribution was provided directly to me by some other
person who certified (a), (b) or (c) and I have not modified
it.
(d) I understand and agree that this project and the contribution
are public and that a record of the contribution (including all
personal information I submit with it, including my sign-off) is
maintained indefinitely and may be redistributed consistent with
this project or the open source license(s) involved.
```
Then you just add a line to every git commit message:
Signed-off-by: Joe Smith <joe.smith@email.com>
Using your real name (sorry, no pseudonyms or anonymous contributions.)
If you set your `user.name` and `user.email` git configs, you can sign your
commit automatically with `git commit -s`.

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# parallella-hw
PARALLELLA: Supercomputing for Everyone
========================================
This repository contains the board design sources and FPGA HDL sources for
the Parallella board and various accessories.
This repository contains the Parallella board design source files and the FPGA
source files.
## Directory Structure
## Board Files
Contains the hardware design files of the Parallella and associated hardware.
```
boards/ - Board design files, all projects
archive/ - Older boards no longer supported,
proto/ - Zedboard based prototype (Jan 2013)
gen0/ - First Parallella board, too hot (Apr 2013)
gen1.0/ - Solid board, but hdmi wiring bug (Oct 2013)
gen1.1/ - Fully working board (Dec 2013)
libraries/ - Shared schematic and PCB tools libraries
kicad/ - KiCad schematic (.lib/.dcm) and 3D source (.scad/.wrl) libs
adapteva-kicad.pretty/ - KiCad footprint (.mod) library
packages3d/ - 3D models for library parts, with some sources
scripts/ - Adapteva Kicad/BOM scripts in Python
parallella-I/ - Current Parallella-I board schematic and PCB source
constraints/ - Constraints files for board-specific pin locations
docs/ - Docs specific to each board
firmware/ - Low-level firmware (fsbl, u-boot, etc.)
mfg/ - Manufacturing files: Fab Gerbers, Assembly docs
parallella-template - KiCad template files for parallella daughtercards
meta/ - Metadata files for template
parallella-porcupine - Breakout board for Parallella-I
Board | Description
-----------|--------------
[parallella-gen1](boards/parallella-gen1) | Parallella Kickstarter board currently in production
[parallella-template](boards/parallella-template) | KiCad template board for creating daughter cards
[porcupine](boards/porcupine) | Breakout board
[parallella-gen2](boards/parallella-gen2) | The next Parallella board (work in progress...)
fpga/ - FPGA design files and projects
bitstreams/ - Latest generated bitstreams
edk/ - EDK sources
parallella_7010_hdmi/ - EDK for hdmi-enabled 7010-based Parallella
parallella_7020_hdmi/ - EDK for hdmi-enabled 7020-based Parallella
parallella_7010_headless/ - EDK for headless 7010-based Parallella
parallella_7020_headless/ - EDK for headless 7020-based Parallella
edk-vivado/ - PS descriptions for Vivado
parallella_7020_headless/ - EDK for headless 7020-based Parallella
externals/ - Container for external repositories used by our projects
fpgahdl_xilinx/ - Submodule for HDMI library modules from ADI
hdl/ - Verilog source files
axi/ - General AXI interface modules
clocks/ - Clock generation
common/ - General-purpose synchronizers/muxs/debouncers/etc.
elink/ - eLink modules
fifos/ - technology-independent FIFO modules
gpio/ - modules for GPIO pins
parallella-I/ - Modules specific to the Parallella
ip/ - Tool-specific IP generation (CoreGen) sources
projects/ - One folder for each project
parallella_64_7020_hdmi/
parallella_64_7020_headless/
parallella_7020_hdmi/
parallella_7010_hdmi/
parallella_7020_headless/
parallella_7010_headless/
projects-vivado/ - Vivado versions of projects
parallella_7020_headless/
```
## FPGA Sources
The table below contains links to some of the key blocks used by the Parallella. All source can be found in "fpga/src"
## FPGA Project Build instructions
Board | Description
-----------|--------------
[elink](src/elink/hdl/elink.v) | Top level of elink physical interface used by the Epiphany
[ecfg](src/ecfg/hdl/ecfg.v) | elink configuration register file
[erx](src/erx/hdl/erx.v) | elink receiver
[etx](src/etx/hdl/etx.v) | elink transmitter
[embox](src/embox/hdl/embox.v) | Fifo based mailbox with interrupt output
[emmu](src/emmu/hdl/emmu.v) | Memory address translation unit
[emaxi](src/axi/hdl/emaxi.v) | AXI master interface
[esaxi](src/axi/hdl/esaxi.v) | AXI slave interface
See README files in the individual project directories.
## FPGA Projects
## License
Unless otherwise specified the parallella-hw project uses the GPLv3 for RTL code and
Creative Common Share Alike for board design files. The GPLv3 license notice can be found at the bottom of the file.
COPYING - GNU GENERAL PUBLIC LICENSE file
##Contribution
We are looking for external contribution to to the Parallella project! If you have something to contribute in the area of board, system, FPGA design, dig in! All pull requests will be considered. Instructions for contributing can be found [HERE](CONTRIBUTING.md).