Reorg

2025-04-01 00:26:53 +00:00 · 2017-01-07 12:50:44 -05:00 · 2017-01-07 12:50:44 -05:00 · af1d6ec597
commit af1d6ec597
parent cbdf1d17f4
16 changed files with 6 additions and 3720 deletions
--- a/meta-module/docs/meta_pinout.xlsx
+++ b/meta-module/docs/meta_pinout.xlsx
--- a/meta-module/docs/meta_planning.xlsx
+++ b/meta-module/docs/meta_planning.xlsx
--- a/meta-module/docs/parallella_meta_spec.odt
+++ b/meta-module/docs/parallella_meta_spec.odt
--- a/meta-module/docs/parallella_meta_spec.pdf
+++ b/meta-module/docs/parallella_meta_spec.pdf
--- a/meta-module/docs/pc104_spec.pdf
+++ b/meta-module/docs/pc104_spec.pdf
--- a/meta-module/docs/snow16.png
+++ b/meta-module/docs/snow16.png
--- a/meta-module/docs/snow16.svg
+++ b/meta-module/docs/snow16.svg
--- a/meta-module/docs/snow4.png
+++ b/meta-module/docs/snow4.png
--- a/meta-module/docs/snow4.svg
+++ b/meta-module/docs/snow4.svg
--- a/meta/docs/meta_arch.svg
+++ b/meta/docs/meta_arch.svg
--- a/meta/docs/meta_mechanical.svg
+++ b/meta/docs/meta_mechanical.svg
--- a/parallella/README.md
+++ b/parallella/README.md
@ -3,11 +3,11 @@ Parallella

 ## Summary

-* Credit card sized SBC
+* Credit card sized Single Board Computer
 * Adapteva 16-core Epiphany RISC 
-* Xilinx Zynq (FPGA+ARM)
-* 1GB SDRAM
-* Gigabit Ethernet, HDMI, USB 2.0, uSD card 
+* Xilinx Zynq FPGA 
+* 1GB DDR3 RAM
+* Gigabit Ethernet, HDMI, USB 2.0, micro-SD
 * 48 GPIO pins
 * 96 elink pins
 * <5W peak power
@ -32,12 +32,12 @@ Licensed under Creative Commons Attribution-Share Alike 3.0 Unprotected License

 ## Status

-In production. 20,000 units built
+In production. >20,000 built

 ## Authors

 * [Andreas Olofsson](https://github.com/aolofsson)
-* [Boston Design Solutions](http://www.bostondesignsolutions.com) (layout)
+* [Boston Design Solutions](http://www.bostondesignsolutions.com)


 ## Images
--- a/parallella/parallella_bom.xls
+++ b/parallella/parallella_bom.xls
--- a/parallella/src/parallella_bom.xls
+++ b/parallella/src/parallella_bom.xls
--- a/parallella/src/parallella_layout.brd
+++ b/parallella/src/parallella_layout.brd
--- a/parallella/src/parallella_schematic.dsn
+++ b/parallella/src/parallella_schematic.dsn