AllSpiceMirrors/parallella-hw
7
Fork 0
mirror of https://github.com/parallella/parallella-hw.git synced 2025-04-17 19:08:55 +00:00
Files Issues Releases Activity
172 Commits 5 Branches 0 Tags 232 MiB
march23
Commit Graph

172 Commits

Author SHA1 Message Date
Andreas Olofsson
bc9a58b48b Merge remote-tracking branch 'origin/elink_redesign_fred' 
Conflicts:
	fpga/src/ecfg/hdl/ecfg.v
	fpga/src/gpio/hdl/parallella_gpio_emio.v
 2015-03-23 15:29:55 -04:00
Andreas Olofsson
862ce4485e Merge remote-tracking branch 'origin/elink_redesign' 2015-03-23 15:24:38 -04:00
Andreas Olofsson
89a0a78cbf Adding the latest Vivado design archive for Parallella 2015-03-21 10:14:13 -04:00
Andreas Olofsson
572e1f5bc2 Shortening names (reorg) 2015-03-21 10:04:55 -04:00
Andreas Olofsson
7f9d1fc4c2 Reorg 2015-03-21 10:01:08 -04:00
Andreas Olofsson
400b3e0d2b Merge pull request from Fred3/master 
Looks good.
 2015-02-22 23:12:07 -05:00
Fred Huettig
97bd47e18b Porcupine Version 2. 2015-02-19 01:07:24 -05:00
Fred Huettig
9dfa677aaf Merge branch 'master' of https://github.com/Parallella/parallella-hw 2015-02-18 03:07:55 -05:00
Fred Huettig
22f0370088 Revert "Fixing port declarations (thanks Verilator!)" 
This reverts commit 7531044740.
 2015-01-28 14:15:13 -05:00
Fred Huettig
ac3a5ffa54 Partial integration of new elink 2015-01-28 13:53:09 -05:00
Fred Huettig
f5193374b7 Added XDC constraints files. 
Added REMAP function to non-MMU eDistrib.
Fixed EMAXI operation when eLink is very busy.
Added streaming support for eproto_rx.
Fixed handling of bursts on ESAXI, added support for memcpy() unaligned reads.
Added testbench code.
 2014-12-19 16:15:26 -05:00
aolofsson
7531044740 Fixing port declarations (thanks Verilator!) 2014-12-15 16:39:28 -05:00
aolofsson
dc7225fddd Fixed renaming bug in e_tx_ack signal. (thanks verilator) 2014-12-15 15:28:33 -05:00
aolofsson
1b24a912b3 Wrong bus width (just cleanup..) 2014-12-15 15:26:07 -05:00
aolofsson
5bc1fff358 Verilator inspired bug fixes 
-address width in elink
-bus widths in ecfg
-command file more generic
 2014-12-15 15:25:09 -05:00
aolofsson
14cbe0ebef Verious silly compilation fixes, nothing to see here.. 2014-12-14 22:24:16 -05:00
aolofsson
1d66006464 Consolidating all axi interface in one directory 
Adding interface for axi lite slave, needs content
 2014-12-14 22:22:49 -05:00
aolofsson
3d31e6dea9 Adding stubs files for xilinx IP 
Goal is to create models for all of these
 2014-12-14 22:21:01 -05:00
aolofsson
65afbb89c0 Adding new elink top level file written in verilog. 
Compiles and runs (needs work)
 2014-12-14 22:19:02 -05:00
aolofsson
cfcfc80593 Adding fofo environment for elink to check for broken signals. 
Too many stub modules to be practical..next need sim models
 2014-12-14 22:17:23 -05:00
aolofsson
082a1c57a1 Moving file to elink (makes more sense): 
Each directory should be a self contained "object"
 2014-12-14 17:41:07 -05:00
aolofsson
21b640003a Adding README file describing design structure of the elink 2014-12-14 17:40:23 -05:00
aolofsson
c1031421d3 An unverified clean top level elink design module 2014-12-14 17:25:46 -05:00
aolofsson
8e0a6e1345 Adding new verilog modules for receiver and transmitter 
-moving away from Vivado block editor
-creating a "clean" split between RX and TX
 2014-12-14 17:18:53 -05:00
aolofsson
dd54ea4eeb Adding axi lite interface to be used by various registers 2014-12-14 17:17:04 -05:00
aolofsson
3c6920571e Incremental renaming 2014-12-14 09:14:25 -05:00
aolofsson
f7c6155d54 Created a verilog wrapper for the elink transmitter 
(moving away from the Vivado block editor)
 2014-12-12 20:36:15 -05:00
aolofsson
ffc2dda821 Changed module name for new structure 2014-12-12 16:35:59 -05:00
aolofsson
b1c6c0b651 Renamed file 
Converted all signals to lower case
 2014-12-12 16:34:52 -05:00
aolofsson
a49875299e Removing old files not needed by new design 2014-12-12 12:27:22 -05:00
aolofsson
9d466a6f1b Add register definition for ESYSDEBUG... 2014-12-12 12:20:18 -05:00
aolofsson
f4be5e7237 Adding a read only debug register for monitor important elink signals. 
Useful for debugging new hardware.
 2014-12-11 14:51:09 -05:00
Fred Huettig
24ae857f9d Minor fixes for implementation. 2014-11-24 01:57:57 -05:00
Fred Huettig
4aed853348 eCfg: Renamed reset input to hw_reset, OR'd into ecfg_reset output. 
eCfg IP updated to match.
 2014-11-19 16:59:04 -05:00
Fred Huettig
8d34b3ca8c Added elink-gold -> elink2 test project. 2014-11-19 14:56:33 -05:00
Fred Huettig
41b14f77f8 Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign 
Conflicts:
	fpga/src/ecfg/hdl/ecfg.v
 2014-11-19 12:29:35 -05:00
Fred Huettig
635227356a New Vivado-friendly modules, testbench for elink gold-vs-new. 2014-11-19 12:02:18 -05:00
aolofsson
da805cf66f Deleting old files (moved to src) 2014-11-06 15:41:28 -05:00
aolofsson
e2267a3919 Cleaning up old files.. 2014-11-06 15:40:40 -05:00
aolofsson
ec4d87939f More file organization 
Adding some more utility functions
 2014-11-06 12:19:39 -05:00
aolofsson
840ccb59b5 A "complete" elink top level block with all new features added. Still need 
to work on the axi side.
 2014-11-06 12:18:16 -05:00
aolofsson
be8b1cf19e Adding place holders for hard macros 2014-11-06 12:17:56 -05:00
aolofsson
6cee5d6ddb Fixing interface as 20 bits, fits with Epiphany architecture. 
Very unlikely to EVER change, so hard coding.
 2014-11-06 12:17:09 -05:00
aolofsson
4842ed7b48 Basic interfaces..still need to add the axi signals and fill in the content 2014-11-06 12:16:09 -05:00
aolofsson
2fffe9944c Adding readback indicator for slave axi mux 2014-11-06 12:15:19 -05:00
aolofsson
a045ce3fa5 Adding readback indicator for AXI slave mux 2014-11-06 12:14:49 -05:00
aolofsson
09f15054b9 Create combined reset (hw+sw) 
Added data select output for axi_slave mux
Signal cleanup (gpio_data)
 2014-11-06 11:52:38 -05:00
aolofsson
250a9e28ca Adding run.sh files for simulation 2014-11-05 20:00:57 -05:00
aolofsson
728bba33b9 Changing to 20 bit address interface 2014-11-05 19:59:15 -05:00
aolofsson
ea73ffcf8f Changed to 20 bit addressing for clarity in FPGA 2014-11-05 19:49:18 -05:00