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12 lines
275 B
Plaintext
12 lines
275 B
Plaintext
***Design Hiearchy***
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parallella.v - Top level file (start here)
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-axi_slave - AXI slave interface for the Zynq
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-ax_master - AXI master interface for the Zynq
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-ewrapper_link_top - eLink wrapper module
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-axi_elink_if - AXI<-->eLink interface module
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