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Andreas Olofsson 046706db8a Reorg
2016-02-03 00:43:14 -05:00
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axi_elink_if.v Reorg 2016-02-03 00:43:14 -05:00
axi_master_rd.v Reorg 2016-02-03 00:43:14 -05:00
axi_master_wr.v Reorg 2016-02-03 00:43:14 -05:00
axi_master.v Reorg 2016-02-03 00:43:14 -05:00
axi_slave_addrch.v Reorg 2016-02-03 00:43:14 -05:00
axi_slave_rd.v Reorg 2016-02-03 00:43:14 -05:00
axi_slave_wr.v Reorg 2016-02-03 00:43:14 -05:00
axi_slave.v Reorg 2016-02-03 00:43:14 -05:00
debouncer.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_io_rx_slow.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_io_tx_slow.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_link_receiver.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_link_rxi.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_link_top.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_link_transmitter.v Reorg 2016-02-03 00:43:14 -05:00
ewrapper_link_txo.v Reorg 2016-02-03 00:43:14 -05:00
fifo_empty_block.v Reorg 2016-02-03 00:43:14 -05:00
fifo_full_block.v Reorg 2016-02-03 00:43:14 -05:00
fifo_mem.v Reorg 2016-02-03 00:43:14 -05:00
fifo.v Reorg 2016-02-03 00:43:14 -05:00
fpga_constants.v Reorg 2016-02-03 00:43:14 -05:00
fpgacfg.v Reorg 2016-02-03 00:43:14 -05:00
mux4.v Reorg 2016-02-03 00:43:14 -05:00
parallella_7020_top.v Reorg 2016-02-03 00:43:14 -05:00
parallella.v Reorg 2016-02-03 00:43:14 -05:00
pulse2pulse.v Reorg 2016-02-03 00:43:14 -05:00
pulse2toggle.v Reorg 2016-02-03 00:43:14 -05:00
README Reorg 2016-02-03 00:43:14 -05:00
synchronizer.v Reorg 2016-02-03 00:43:14 -05:00
toggle2pulse.v Reorg 2016-02-03 00:43:14 -05:00
version.v Reorg 2016-02-03 00:43:14 -05:00

README 

***Design Hiearchy***
parallella.v		- Top level file (start here)
  -axi_slave	      	- AXI slave interface for the Zynq
  -ax_master	      	- AXI master interface for the Zynq
  -ewrapper_link_top	- eLink wrapper module
  -axi_elink_if		- AXI<-->eLink interface module