mirror of
https://github.com/parallella/parallella-hw.git
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650 lines
29 KiB
Verilog
650 lines
29 KiB
Verilog
/*
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File: parallella.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module parallella (/*AUTOARG*/
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// Outputs
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csysack, cactive, reset_chip, reset_fpga, txo_data_p, txo_data_n,
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txo_frame_p, txo_frame_n, txo_lclk_p, txo_lclk_n, rxi_wr_wait_p,
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rxi_wr_wait_n, rxi_rd_wait_p, rxi_rd_wait_n, rxi_cclk_p,
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rxi_cclk_n, emaxi_awid, emaxi_awaddr, emaxi_awlen, emaxi_awsize,
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emaxi_awburst, emaxi_awlock, emaxi_awcache, emaxi_awprot,
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emaxi_awvalid, esaxi_awready, emaxi_wid, emaxi_wdata, emaxi_wstrb,
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emaxi_wlast, emaxi_wvalid, esaxi_wready, emaxi_bready, esaxi_bid,
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esaxi_bresp, esaxi_bvalid, emaxi_arid, emaxi_araddr, emaxi_arlen,
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emaxi_arsize, emaxi_arburst, emaxi_arlock, emaxi_arcache,
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emaxi_arprot, emaxi_arvalid, esaxi_arready, emaxi_rready,
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esaxi_rid, esaxi_rdata, esaxi_rresp, esaxi_rlast, esaxi_rvalid,
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emaxi_awqos, emaxi_arqos,
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// Inputs
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clkin_100, esaxi_aclk, emaxi_aclk, reset, esaxi_aresetn,
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emaxi_aresetn, csysreq, rxi_data_p, rxi_data_n, rxi_frame_p,
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rxi_frame_n, rxi_lclk_p, rxi_lclk_n, txo_wr_wait_p, txo_wr_wait_n,
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txo_rd_wait_p, txo_rd_wait_n, emaxi_awready, esaxi_awid,
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esaxi_awaddr, esaxi_awlen, esaxi_awsize, esaxi_awburst,
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esaxi_awlock, esaxi_awcache, esaxi_awprot, esaxi_awvalid,
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emaxi_wready, esaxi_wid, esaxi_wdata, esaxi_wstrb, esaxi_wlast,
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esaxi_wvalid, emaxi_bid, emaxi_bresp, emaxi_bvalid, esaxi_bready,
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emaxi_arready, esaxi_arid, esaxi_araddr, esaxi_arlen, esaxi_arsize,
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esaxi_arburst, esaxi_arlock, esaxi_arcache, esaxi_arprot,
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esaxi_arvalid, emaxi_rid, emaxi_rdata, emaxi_rresp, emaxi_rlast,
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emaxi_rvalid, esaxi_rready, esaxi_awqos, esaxi_arqos
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);
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parameter SIDW = 12; //ID Width
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parameter SAW = 32; //Address Bus Width
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parameter SDW = 32; //Data Bus Width
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parameter MIDW = 6; //ID Width
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parameter MAW = 32; //Address Bus Width
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parameter MDW = 64; //Data Bus Width
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parameter STW = 8; //Number of strobes
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parameter LW = 8;
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parameter AW = 32; //Address Bus Width
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parameter DW = 32; //Data Bus Width
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//#########
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//# Inputs
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//#########
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// global signals
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input clkin_100; // 100MHz input clock
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input esaxi_aclk; // clock source of the axi bus for slave port
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input emaxi_aclk; // clock source of the axi bus for master port
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input reset; // system reset
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input esaxi_aresetn; // reset of axi bus for slave port
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input emaxi_aresetn; // reset of axi bus for master port
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input csysreq; // system exit low-power state request
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// LVDS FMC Port
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input [7:0] rxi_data_p;
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input [7:0] rxi_data_n;
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input rxi_frame_p;
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input rxi_frame_n;
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input rxi_lclk_p;
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input rxi_lclk_n;
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input txo_wr_wait_p;
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input txo_wr_wait_n;
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input txo_rd_wait_p;
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input txo_rd_wait_n;
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//########################
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//# Write address channel
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//########################
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// Master Port
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input emaxi_awready; //write address ready
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// Slave Port
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input [SIDW-1:0] esaxi_awid; //write address ID
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input [MAW-1:0] esaxi_awaddr; //write address
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input [3:0] esaxi_awlen; //burst lenght (the number of data transfers)
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input [2:0] esaxi_awsize; //burst size (the size of each transfer)
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input [1:0] esaxi_awburst; //burst type
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input [1:0] esaxi_awlock; //lock type (atomic characteristics)
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input [3:0] esaxi_awcache; //memory type
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input [2:0] esaxi_awprot; //protection type
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input esaxi_awvalid; //write address valid
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//########################
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//# Write data channel
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//########################
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// Master Port
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input emaxi_wready;//write ready
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// Slave Port
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input [SIDW-1:0] esaxi_wid; //write ID tag (supported only in AXI3)
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input [SDW-1:0] esaxi_wdata; //write data
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input [3:0] esaxi_wstrb; //write strobes
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input esaxi_wlast; //write last. Indicates last transfer in burst
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input esaxi_wvalid;//write valid
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//########################
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// Write response channel
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//########################
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// Master Port
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input [MIDW-1:0] emaxi_bid; //response ID tag
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input [1:0] emaxi_bresp; //write response
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input emaxi_bvalid;//write response valid
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// Slave Port
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input esaxi_bready;//response ready
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//########################
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//# Read address channel
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//########################
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// Master Port
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input emaxi_arready;//read address ready
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// Slave Port
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input [SIDW-1:0] esaxi_arid; //read address ID
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input [MAW-1:0] esaxi_araddr; //read address
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input [3:0] esaxi_arlen; //burst lenght (the number of data transfers)
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input [2:0] esaxi_arsize; //burst size (the size of each transfer)
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input [1:0] esaxi_arburst; //burst type
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input [1:0] esaxi_arlock; //lock type (atomic characteristics)
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input [3:0] esaxi_arcache; //memory type
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input [2:0] esaxi_arprot; //protection type
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input esaxi_arvalid; //write address valid
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//########################
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//# Read data channel
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//########################
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// Master Port
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input [MIDW-1:0] emaxi_rid; //read ID tag
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input [MDW-1:0] emaxi_rdata; //read data
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input [1:0] emaxi_rresp; //read response
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input emaxi_rlast; //read last, indicates last transfer in burst
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input emaxi_rvalid;//read valid
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// Slave Port
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input esaxi_rready; //read ready
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//##########
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//# Outputs
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//##########
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// global signals
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output csysack;//exit low-power state acknowledgement
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output cactive;//clock active
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output reset_chip;
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output reset_fpga;
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// LVDS FMC Port
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output [7:0] txo_data_p;
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output [7:0] txo_data_n;
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output txo_frame_p;
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output txo_frame_n;
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output txo_lclk_p;
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output txo_lclk_n;
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output rxi_wr_wait_p;
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output rxi_wr_wait_n;
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output rxi_rd_wait_p;
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output rxi_rd_wait_n;
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output rxi_cclk_p;
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output rxi_cclk_n;
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//########################
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//# Write address channel
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//########################
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// Master Port
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output [MIDW-1:0] emaxi_awid; //write address ID
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output [MAW-1:0] emaxi_awaddr; //write address
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output [3:0] emaxi_awlen; //burst length (number of data transfers)
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output [2:0] emaxi_awsize; //burst size (the size of each transfer)
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output [1:0] emaxi_awburst; //burst type
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output [1:0] emaxi_awlock; //lock type (atomic characteristics)
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output [3:0] emaxi_awcache; //memory type
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output [2:0] emaxi_awprot; //protection type
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output emaxi_awvalid; //write address valid
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// Slave Port
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output esaxi_awready; //write address ready
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//########################
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//# Write data channel
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//########################
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// Master Port
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output [MIDW-1:0] emaxi_wid; //write ID tag (supported only in AXI3)
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output [MDW-1:0] emaxi_wdata; //write data
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output [STW-1:0] emaxi_wstrb; //write strobes
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output emaxi_wlast; //write last, indicates last transfer in burst
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output emaxi_wvalid;//write valid
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// Slave Port
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output esaxi_wready;//write ready
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//########################
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// Write response channel
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//########################
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// Master Port
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output emaxi_bready;//response ready
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// Slave Port
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output [SIDW-1:0] esaxi_bid; //response ID tag
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output [1:0] esaxi_bresp; //write response
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output esaxi_bvalid;//write response valid
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//########################
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//# Read address channel
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//########################
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// Master Port
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output [MIDW-1:0] emaxi_arid; //read address ID
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output [MAW-1:0] emaxi_araddr; //read address
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output [3:0] emaxi_arlen; //burst lenght (number of data transfers)
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output [2:0] emaxi_arsize; //burst size (the size of each transfer)
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output [1:0] emaxi_arburst; //burst type
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output [1:0] emaxi_arlock; //lock type (atomic characteristics)
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output [3:0] emaxi_arcache; //memory type
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output [2:0] emaxi_arprot; //protection type
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output emaxi_arvalid; //write address valid
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// Slave Port
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output esaxi_arready; //read address ready
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//########################
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//# Read data channel
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//########################
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// Master Port
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output emaxi_rready; //read ready
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// Slave Port
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output [SIDW-1:0] esaxi_rid; //read ID tag (must match arid of transaction)
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output [SDW-1:0] esaxi_rdata; //read data
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output [1:0] esaxi_rresp; //read response
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output esaxi_rlast; //read last, indicates last transfer in burst
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output esaxi_rvalid;//read valid
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//#######################################################################
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//# The following features are not supported (AXI4 only)
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//# If un-commented, those signals have to be driven with default values
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//#######################################################################
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// input emaxi_buser; //user signal
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// input emaxi_ruser; //user signal
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output [3:0] emaxi_awqos; //quality of service default 4'b0000
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// output [3:0] emaxi_awregion;//region identifier
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// output emaxi_awuser; //user signal
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// output emaxi_wuser; //user signal
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output [3:0] emaxi_arqos; //quality of service default 4'b0000
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// output [3:0] emaxi_arregion;//region identifier
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// output emaxi_aruser; //user signal
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input [3:0] esaxi_awqos; //Quality of Service default 4'b0000
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// input [3:0] awregion; //region identifier
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// input awuser; //user signal
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// input wuser; //user signal
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input [3:0] esaxi_arqos; //quality of service default 4'b0000
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// input [3:0] arregion; //region identifier (AXI4 only)
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// input aruser; //user signal (AXI4 only)
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// output buser; //user signal (AXI4 only)
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// output ruser; //user signal (AXI4 only)
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire elink_access_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire elink_access_outb; // From axi_elink_if of axi_elink_if.v
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wire [3:0] elink_ctrlmode_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire [3:0] elink_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] elink_data_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire [31:0] elink_data_outb; // From axi_elink_if of axi_elink_if.v
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wire [1:0] elink_datamode_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire [1:0] elink_datamode_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] elink_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
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wire elink_rd_wait_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire elink_rd_wait_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] elink_srcaddr_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire [31:0] elink_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
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wire elink_wr_wait_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire elink_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
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wire elink_write_inb; // From ewrapper_link_top of ewrapper_link_top.v
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wire elink_write_outb; // From axi_elink_if of axi_elink_if.v
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wire emaxi_access_inb; // From axi_master of axi_master.v
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wire emaxi_access_outb; // From axi_elink_if of axi_elink_if.v
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wire [3:0] emaxi_ctrlmode_inb; // From axi_master of axi_master.v
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wire [3:0] emaxi_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] emaxi_data_inb; // From axi_master of axi_master.v
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wire [31:0] emaxi_data_outb; // From axi_elink_if of axi_elink_if.v
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wire [1:0] emaxi_datamode_inb; // From axi_master of axi_master.v
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wire [1:0] emaxi_datamode_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] emaxi_dstaddr_inb; // From axi_master of axi_master.v
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wire [31:0] emaxi_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
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wire emaxi_rd_wait_inb; // From axi_master of axi_master.v
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wire [31:0] emaxi_srcaddr_inb; // From axi_master of axi_master.v
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wire [31:0] emaxi_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
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wire emaxi_wr_wait_inb; // From axi_master of axi_master.v
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wire emaxi_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
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wire emaxi_write_inb; // From axi_master of axi_master.v
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wire emaxi_write_outb; // From axi_elink_if of axi_elink_if.v
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wire esaxi_access_inb; // From axi_slave of axi_slave.v
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wire esaxi_access_outb; // From axi_elink_if of axi_elink_if.v
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wire [3:0] esaxi_ctrlmode_inb; // From axi_slave of axi_slave.v
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wire [3:0] esaxi_ctrlmode_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] esaxi_data_inb; // From axi_slave of axi_slave.v
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wire [31:0] esaxi_data_outb; // From axi_elink_if of axi_elink_if.v
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wire [1:0] esaxi_datamode_inb; // From axi_slave of axi_slave.v
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wire [1:0] esaxi_datamode_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] esaxi_dstaddr_inb; // From axi_slave of axi_slave.v
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wire [31:0] esaxi_dstaddr_outb; // From axi_elink_if of axi_elink_if.v
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wire esaxi_rd_wait_inb; // From axi_slave of axi_slave.v
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wire esaxi_rd_wait_outb; // From axi_elink_if of axi_elink_if.v
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wire [31:0] esaxi_srcaddr_inb; // From axi_slave of axi_slave.v
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wire [31:0] esaxi_srcaddr_outb; // From axi_elink_if of axi_elink_if.v
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wire esaxi_wr_wait_inb; // From axi_slave of axi_slave.v
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wire esaxi_wr_wait_outb; // From axi_elink_if of axi_elink_if.v
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wire esaxi_write_inb; // From axi_slave of axi_slave.v
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wire esaxi_write_outb; // From axi_elink_if of axi_elink_if.v
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// End of automatics
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//#########
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//# Regs
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//#########
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//#########
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//# Wires
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//#########
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wire emaxi_reset;
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wire esaxi_reset;
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wire rxi_eclk;
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wire [31:0] elink_dstaddr_inb;
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wire [31:0] elink_dstaddr_tmp;
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wire ext_mem_access;
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//#################
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//# global signals
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//#################
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assign emaxi_reset = ~emaxi_aresetn;
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assign esaxi_reset = ~esaxi_aresetn;
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//##################################
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//# AXI Slave Port Instantiation
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//##################################
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/*axi_slave AUTO_TEMPLATE(.eclk (rxi_eclk),
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.reset (esaxi_reset),
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.aclk (esaxi_aclk),
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.aw\(.*\) (esaxi_aw\1[]),
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.w\(.*\) (esaxi_w\1[]),
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.b\(.*\) (esaxi_b\1[]),
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.ar\(.*\) (esaxi_ar\1[]),
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.r\(.*\) (esaxi_r\1[]),
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.emesh_\(.*\) (esaxi_\1[]),
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);
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*/
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axi_slave axi_slave(/*AUTOINST*/
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// Outputs
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.csysack (csysack),
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.cactive (cactive),
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.awready (esaxi_awready), // Templated
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.wready (esaxi_wready), // Templated
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.bid (esaxi_bid[SIDW-1:0]), // Templated
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.bresp (esaxi_bresp[1:0]), // Templated
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.bvalid (esaxi_bvalid), // Templated
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.arready (esaxi_arready), // Templated
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.rid (esaxi_rid[SIDW-1:0]), // Templated
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.rdata (esaxi_rdata[SDW-1:0]), // Templated
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.rresp (esaxi_rresp[1:0]), // Templated
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.rlast (esaxi_rlast), // Templated
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.rvalid (esaxi_rvalid), // Templated
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.emesh_access_inb(esaxi_access_inb), // Templated
|
|
.emesh_write_inb (esaxi_write_inb), // Templated
|
|
.emesh_datamode_inb(esaxi_datamode_inb[1:0]), // Templated
|
|
.emesh_ctrlmode_inb(esaxi_ctrlmode_inb[3:0]), // Templated
|
|
.emesh_dstaddr_inb(esaxi_dstaddr_inb[31:0]), // Templated
|
|
.emesh_srcaddr_inb(esaxi_srcaddr_inb[31:0]), // Templated
|
|
.emesh_data_inb (esaxi_data_inb[31:0]), // Templated
|
|
.emesh_wr_wait_inb(esaxi_wr_wait_inb), // Templated
|
|
.emesh_rd_wait_inb(esaxi_rd_wait_inb), // Templated
|
|
// Inputs
|
|
.aclk (esaxi_aclk), // Templated
|
|
.eclk (rxi_eclk), // Templated
|
|
.reset (esaxi_reset), // Templated
|
|
.csysreq (csysreq),
|
|
.awid (esaxi_awid[SIDW-1:0]), // Templated
|
|
.awaddr (esaxi_awaddr[SAW-1:0]), // Templated
|
|
.awlen (esaxi_awlen[3:0]), // Templated
|
|
.awsize (esaxi_awsize[2:0]), // Templated
|
|
.awburst (esaxi_awburst[1:0]), // Templated
|
|
.awlock (esaxi_awlock[1:0]), // Templated
|
|
.awcache (esaxi_awcache[3:0]), // Templated
|
|
.awprot (esaxi_awprot[2:0]), // Templated
|
|
.awvalid (esaxi_awvalid), // Templated
|
|
.wid (esaxi_wid[SIDW-1:0]), // Templated
|
|
.wdata (esaxi_wdata[SDW-1:0]), // Templated
|
|
.wstrb (esaxi_wstrb[3:0]), // Templated
|
|
.wlast (esaxi_wlast), // Templated
|
|
.wvalid (esaxi_wvalid), // Templated
|
|
.bready (esaxi_bready), // Templated
|
|
.arid (esaxi_arid[SIDW-1:0]), // Templated
|
|
.araddr (esaxi_araddr[SAW-1:0]), // Templated
|
|
.arlen (esaxi_arlen[3:0]), // Templated
|
|
.arsize (esaxi_arsize[2:0]), // Templated
|
|
.arburst (esaxi_arburst[1:0]), // Templated
|
|
.arlock (esaxi_arlock[1:0]), // Templated
|
|
.arcache (esaxi_arcache[3:0]), // Templated
|
|
.arprot (esaxi_arprot[2:0]), // Templated
|
|
.arvalid (esaxi_arvalid), // Templated
|
|
.rready (esaxi_rready), // Templated
|
|
.emesh_access_outb(esaxi_access_outb), // Templated
|
|
.emesh_write_outb(esaxi_write_outb), // Templated
|
|
.emesh_datamode_outb(esaxi_datamode_outb[1:0]), // Templated
|
|
.emesh_ctrlmode_outb(esaxi_ctrlmode_outb[3:0]), // Templated
|
|
.emesh_dstaddr_outb(esaxi_dstaddr_outb[31:0]), // Templated
|
|
.emesh_srcaddr_outb(esaxi_srcaddr_outb[31:0]), // Templated
|
|
.emesh_data_outb (esaxi_data_outb[31:0]), // Templated
|
|
.emesh_wr_wait_outb(esaxi_wr_wait_outb), // Templated
|
|
.emesh_rd_wait_outb(esaxi_rd_wait_outb), // Templated
|
|
.awqos (esaxi_awqos[3:0]), // Templated
|
|
.arqos (esaxi_arqos[3:0])); // Templated
|
|
|
|
//##################################
|
|
//# AXI Master Port Instantiation
|
|
//##################################
|
|
|
|
/*axi_master AUTO_TEMPLATE(.eclk (rxi_eclk),
|
|
.reset (emaxi_reset),
|
|
.aclk (emaxi_aclk),
|
|
.aw\(.*\) (emaxi_aw\1[]),
|
|
.w\(.*\) (emaxi_w\1[]),
|
|
.b\(.*\) (emaxi_b\1[]),
|
|
.ar\(.*\) (emaxi_ar\1[]),
|
|
.r\(.*\) (emaxi_r\1[]),
|
|
.emesh_\(.*\) (emaxi_\1[]),
|
|
);
|
|
*/
|
|
|
|
axi_master axi_master(/*AUTOINST*/
|
|
// Outputs
|
|
.awid (emaxi_awid[MIDW-1:0]), // Templated
|
|
.awaddr (emaxi_awaddr[MAW-1:0]), // Templated
|
|
.awlen (emaxi_awlen[3:0]), // Templated
|
|
.awsize (emaxi_awsize[2:0]), // Templated
|
|
.awburst (emaxi_awburst[1:0]), // Templated
|
|
.awlock (emaxi_awlock[1:0]), // Templated
|
|
.awcache (emaxi_awcache[3:0]), // Templated
|
|
.awprot (emaxi_awprot[2:0]), // Templated
|
|
.awvalid (emaxi_awvalid), // Templated
|
|
.wid (emaxi_wid[MIDW-1:0]), // Templated
|
|
.wdata (emaxi_wdata[MDW-1:0]), // Templated
|
|
.wstrb (emaxi_wstrb[STW-1:0]), // Templated
|
|
.wlast (emaxi_wlast), // Templated
|
|
.wvalid (emaxi_wvalid), // Templated
|
|
.bready (emaxi_bready), // Templated
|
|
.arid (emaxi_arid[MIDW-1:0]), // Templated
|
|
.araddr (emaxi_araddr[MAW-1:0]), // Templated
|
|
.arlen (emaxi_arlen[3:0]), // Templated
|
|
.arsize (emaxi_arsize[2:0]), // Templated
|
|
.arburst (emaxi_arburst[1:0]), // Templated
|
|
.arlock (emaxi_arlock[1:0]), // Templated
|
|
.arcache (emaxi_arcache[3:0]), // Templated
|
|
.arprot (emaxi_arprot[2:0]), // Templated
|
|
.arvalid (emaxi_arvalid), // Templated
|
|
.rready (emaxi_rready), // Templated
|
|
.emesh_access_inb (emaxi_access_inb), // Templated
|
|
.emesh_write_inb (emaxi_write_inb), // Templated
|
|
.emesh_datamode_inb (emaxi_datamode_inb[1:0]), // Templated
|
|
.emesh_ctrlmode_inb (emaxi_ctrlmode_inb[3:0]), // Templated
|
|
.emesh_dstaddr_inb (emaxi_dstaddr_inb[31:0]), // Templated
|
|
.emesh_srcaddr_inb (emaxi_srcaddr_inb[31:0]), // Templated
|
|
.emesh_data_inb (emaxi_data_inb[31:0]), // Templated
|
|
.emesh_wr_wait_inb (emaxi_wr_wait_inb), // Templated
|
|
.emesh_rd_wait_inb (emaxi_rd_wait_inb), // Templated
|
|
.awqos (emaxi_awqos[3:0]), // Templated
|
|
.arqos (emaxi_arqos[3:0]), // Templated
|
|
// Inputs
|
|
.aclk (emaxi_aclk), // Templated
|
|
.eclk (rxi_eclk), // Templated
|
|
.reset (emaxi_reset), // Templated
|
|
.awready (emaxi_awready), // Templated
|
|
.wready (emaxi_wready), // Templated
|
|
.bid (emaxi_bid[MIDW-1:0]), // Templated
|
|
.bresp (emaxi_bresp[1:0]), // Templated
|
|
.bvalid (emaxi_bvalid), // Templated
|
|
.arready (emaxi_arready), // Templated
|
|
.rid (emaxi_rid[MIDW-1:0]), // Templated
|
|
.rdata (emaxi_rdata[MDW-1:0]), // Templated
|
|
.rresp (emaxi_rresp[1:0]), // Templated
|
|
.rlast (emaxi_rlast), // Templated
|
|
.rvalid (emaxi_rvalid), // Templated
|
|
.emesh_access_outb (emaxi_access_outb), // Templated
|
|
.emesh_write_outb (emaxi_write_outb), // Templated
|
|
.emesh_datamode_outb (emaxi_datamode_outb[1:0]), // Templated
|
|
.emesh_ctrlmode_outb (emaxi_ctrlmode_outb[3:0]), // Templated
|
|
.emesh_dstaddr_outb (emaxi_dstaddr_outb[31:0]), // Templated
|
|
.emesh_srcaddr_outb (emaxi_srcaddr_outb[31:0]), // Templated
|
|
.emesh_data_outb (emaxi_data_outb[31:0]), // Templated
|
|
.emesh_wr_wait_outb (emaxi_wr_wait_outb)); // Templated
|
|
|
|
//#####################################
|
|
//# ELINK (CHIP Port) Instantiation
|
|
//#####################################
|
|
|
|
//# "manual remapping" of external memory address seen by the chips
|
|
assign ext_mem_access = (elink_dstaddr_tmp[31:28] == `VIRT_EXT_MEM) &
|
|
~(elink_dstaddr_tmp[31:20] == `AXI_COORD);
|
|
|
|
assign elink_dstaddr_inb[31:28] = ext_mem_access ? `PHYS_EXT_MEM :
|
|
elink_dstaddr_tmp[31:28];
|
|
|
|
assign elink_dstaddr_inb[27:0] = elink_dstaddr_tmp[27:0];
|
|
|
|
/*ewrapper_link_top AUTO_TEMPLATE(.emesh_clk_inb (rxi_eclk),
|
|
.reset (reset),
|
|
.clkin_100 (clkin_100),
|
|
.rxi_\(.*\) (rxi_\1[]),
|
|
.txo_\(.*\) (txo_\1[]),
|
|
.burst_en (1'b1),
|
|
.emesh_dstaddr_inb(elink_dstaddr_tmp[31:0]),
|
|
.emesh_\(.*\) (elink_\1[]),
|
|
);
|
|
*/
|
|
|
|
ewrapper_link_top ewrapper_link_top(/*AUTOINST*/
|
|
// Outputs
|
|
.emesh_clk_inb (rxi_eclk), // Templated
|
|
.emesh_access_inb(elink_access_inb), // Templated
|
|
.emesh_write_inb (elink_write_inb), // Templated
|
|
.emesh_datamode_inb(elink_datamode_inb[1:0]), // Templated
|
|
.emesh_ctrlmode_inb(elink_ctrlmode_inb[3:0]), // Templated
|
|
.emesh_dstaddr_inb(elink_dstaddr_tmp[31:0]), // Templated
|
|
.emesh_srcaddr_inb(elink_srcaddr_inb[31:0]), // Templated
|
|
.emesh_data_inb (elink_data_inb[31:0]), // Templated
|
|
.emesh_wr_wait_inb(elink_wr_wait_inb), // Templated
|
|
.emesh_rd_wait_inb(elink_rd_wait_inb), // Templated
|
|
.txo_data_p (txo_data_p[7:0]), // Templated
|
|
.txo_data_n (txo_data_n[7:0]), // Templated
|
|
.txo_frame_p (txo_frame_p), // Templated
|
|
.txo_frame_n (txo_frame_n), // Templated
|
|
.txo_lclk_p (txo_lclk_p), // Templated
|
|
.txo_lclk_n (txo_lclk_n), // Templated
|
|
.rxi_wr_wait_p (rxi_wr_wait_p), // Templated
|
|
.rxi_wr_wait_n (rxi_wr_wait_n), // Templated
|
|
.rxi_rd_wait_p (rxi_rd_wait_p), // Templated
|
|
.rxi_rd_wait_n (rxi_rd_wait_n), // Templated
|
|
.rxi_cclk_p (rxi_cclk_p), // Templated
|
|
.rxi_cclk_n (rxi_cclk_n), // Templated
|
|
// Inputs
|
|
.reset (reset), // Templated
|
|
.clkin_100 (clkin_100), // Templated
|
|
.emesh_access_outb(elink_access_outb), // Templated
|
|
.emesh_write_outb(elink_write_outb), // Templated
|
|
.emesh_datamode_outb(elink_datamode_outb[1:0]), // Templated
|
|
.emesh_ctrlmode_outb(elink_ctrlmode_outb[3:0]), // Templated
|
|
.emesh_dstaddr_outb(elink_dstaddr_outb[31:0]), // Templated
|
|
.emesh_srcaddr_outb(elink_srcaddr_outb[31:0]), // Templated
|
|
.emesh_data_outb (elink_data_outb[31:0]), // Templated
|
|
.emesh_wr_wait_outb(elink_wr_wait_outb), // Templated
|
|
.emesh_rd_wait_outb(elink_rd_wait_outb), // Templated
|
|
.rxi_data_p (rxi_data_p[7:0]), // Templated
|
|
.rxi_data_n (rxi_data_n[7:0]), // Templated
|
|
.rxi_frame_p (rxi_frame_p), // Templated
|
|
.rxi_frame_n (rxi_frame_n), // Templated
|
|
.rxi_lclk_p (rxi_lclk_p), // Templated
|
|
.rxi_lclk_n (rxi_lclk_n), // Templated
|
|
.txo_wr_wait_p (txo_wr_wait_p), // Templated
|
|
.txo_wr_wait_n (txo_wr_wait_n), // Templated
|
|
.txo_rd_wait_p (txo_rd_wait_p), // Templated
|
|
.txo_rd_wait_n (txo_rd_wait_n), // Templated
|
|
.burst_en (1'b1)); // Templated
|
|
|
|
//####################################
|
|
//# AXI-ELINK Interface Instantiation
|
|
//####################################
|
|
|
|
/*axi_elink_if AUTO_TEMPLATE(.eclk (rxi_eclk),
|
|
.aclk (esaxi_aclk),
|
|
);
|
|
*/
|
|
|
|
axi_elink_if axi_elink_if(/*AUTOINST*/
|
|
// Outputs
|
|
.reset_chip (reset_chip),
|
|
.reset_fpga (reset_fpga),
|
|
.emaxi_access_outb (emaxi_access_outb),
|
|
.emaxi_write_outb (emaxi_write_outb),
|
|
.emaxi_datamode_outb(emaxi_datamode_outb[1:0]),
|
|
.emaxi_ctrlmode_outb(emaxi_ctrlmode_outb[3:0]),
|
|
.emaxi_dstaddr_outb(emaxi_dstaddr_outb[31:0]),
|
|
.emaxi_srcaddr_outb(emaxi_srcaddr_outb[31:0]),
|
|
.emaxi_data_outb (emaxi_data_outb[31:0]),
|
|
.emaxi_wr_wait_outb(emaxi_wr_wait_outb),
|
|
.esaxi_access_outb (esaxi_access_outb),
|
|
.esaxi_write_outb (esaxi_write_outb),
|
|
.esaxi_datamode_outb(esaxi_datamode_outb[1:0]),
|
|
.esaxi_ctrlmode_outb(esaxi_ctrlmode_outb[3:0]),
|
|
.esaxi_dstaddr_outb(esaxi_dstaddr_outb[31:0]),
|
|
.esaxi_srcaddr_outb(esaxi_srcaddr_outb[31:0]),
|
|
.esaxi_data_outb (esaxi_data_outb[31:0]),
|
|
.esaxi_wr_wait_outb(esaxi_wr_wait_outb),
|
|
.esaxi_rd_wait_outb(esaxi_rd_wait_outb),
|
|
.elink_access_outb (elink_access_outb),
|
|
.elink_write_outb (elink_write_outb),
|
|
.elink_datamode_outb(elink_datamode_outb[1:0]),
|
|
.elink_ctrlmode_outb(elink_ctrlmode_outb[3:0]),
|
|
.elink_dstaddr_outb(elink_dstaddr_outb[31:0]),
|
|
.elink_srcaddr_outb(elink_srcaddr_outb[31:0]),
|
|
.elink_data_outb (elink_data_outb[31:0]),
|
|
.elink_wr_wait_outb(elink_wr_wait_outb),
|
|
.elink_rd_wait_outb(elink_rd_wait_outb),
|
|
// Inputs
|
|
.eclk (rxi_eclk), // Templated
|
|
.aclk (esaxi_aclk), // Templated
|
|
.reset (reset),
|
|
.emaxi_access_inb (emaxi_access_inb),
|
|
.emaxi_write_inb (emaxi_write_inb),
|
|
.emaxi_datamode_inb(emaxi_datamode_inb[1:0]),
|
|
.emaxi_ctrlmode_inb(emaxi_ctrlmode_inb[3:0]),
|
|
.emaxi_dstaddr_inb (emaxi_dstaddr_inb[31:0]),
|
|
.emaxi_srcaddr_inb (emaxi_srcaddr_inb[31:0]),
|
|
.emaxi_data_inb (emaxi_data_inb[31:0]),
|
|
.emaxi_wr_wait_inb (emaxi_wr_wait_inb),
|
|
.emaxi_rd_wait_inb (emaxi_rd_wait_inb),
|
|
.esaxi_access_inb (esaxi_access_inb),
|
|
.esaxi_write_inb (esaxi_write_inb),
|
|
.esaxi_datamode_inb(esaxi_datamode_inb[1:0]),
|
|
.esaxi_ctrlmode_inb(esaxi_ctrlmode_inb[3:0]),
|
|
.esaxi_dstaddr_inb (esaxi_dstaddr_inb[31:0]),
|
|
.esaxi_srcaddr_inb (esaxi_srcaddr_inb[31:0]),
|
|
.esaxi_data_inb (esaxi_data_inb[31:0]),
|
|
.esaxi_wr_wait_inb (esaxi_wr_wait_inb),
|
|
.esaxi_rd_wait_inb (esaxi_rd_wait_inb),
|
|
.elink_access_inb (elink_access_inb),
|
|
.elink_write_inb (elink_write_inb),
|
|
.elink_datamode_inb(elink_datamode_inb[1:0]),
|
|
.elink_ctrlmode_inb(elink_ctrlmode_inb[3:0]),
|
|
.elink_dstaddr_inb (elink_dstaddr_inb[31:0]),
|
|
.elink_srcaddr_inb (elink_srcaddr_inb[31:0]),
|
|
.elink_data_inb (elink_data_inb[31:0]),
|
|
.elink_wr_wait_inb (elink_wr_wait_inb),
|
|
.elink_rd_wait_inb (elink_rd_wait_inb));
|
|
|
|
endmodule // parallella
|