mirror of
https://github.com/parallella/parallella-hw.git
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355 lines
12 KiB
Verilog
355 lines
12 KiB
Verilog
/*
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File: ewrapper_link_top.v
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This file is part of the Parallella Project
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module ewrapper_link_top (/*AUTOARG*/
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// Outputs
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emesh_clk_inb, emesh_access_inb, emesh_write_inb,
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emesh_datamode_inb, emesh_ctrlmode_inb, emesh_dstaddr_inb,
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emesh_srcaddr_inb, emesh_data_inb, emesh_wr_wait_inb,
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emesh_rd_wait_inb, txo_data_p, txo_data_n, txo_frame_p,
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txo_frame_n, txo_lclk_p, txo_lclk_n, rxi_wr_wait_p, rxi_wr_wait_n,
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rxi_rd_wait_p, rxi_rd_wait_n, rxi_cclk_p, rxi_cclk_n,
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// Inputs
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reset, clkin_100, emesh_access_outb, emesh_write_outb,
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emesh_datamode_outb, emesh_ctrlmode_outb, emesh_dstaddr_outb,
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emesh_srcaddr_outb, emesh_data_outb, emesh_wr_wait_outb,
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emesh_rd_wait_outb, rxi_data_p, rxi_data_n, rxi_frame_p,
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rxi_frame_n, rxi_lclk_p, rxi_lclk_n, txo_wr_wait_p, txo_wr_wait_n,
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txo_rd_wait_p, txo_rd_wait_n, burst_en
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);
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//#############
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//# INPUTS
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//#############
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input reset;
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input clkin_100;
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//# From the emesh interface
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input emesh_access_outb;
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input emesh_write_outb;
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input [1:0] emesh_datamode_outb;
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input [3:0] emesh_ctrlmode_outb;
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input [31:0] emesh_dstaddr_outb;
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input [31:0] emesh_srcaddr_outb;
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input [31:0] emesh_data_outb;
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input emesh_wr_wait_outb;
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input emesh_rd_wait_outb;
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//# From the chip (hsmc port)
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input [7:0] rxi_data_p;
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input [7:0] rxi_data_n;
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input rxi_frame_p;
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input rxi_frame_n;
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input rxi_lclk_p;
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input rxi_lclk_n;
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input txo_wr_wait_p;
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input txo_wr_wait_n;
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input txo_rd_wait_p;
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input txo_rd_wait_n;
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input burst_en; // Burst enable control
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//###################
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//# OUTPUTS
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//###################
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//# To the emesh interface
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output emesh_clk_inb;
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output emesh_access_inb;
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output emesh_write_inb;
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output [1:0] emesh_datamode_inb;
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output [3:0] emesh_ctrlmode_inb;
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output [31:0] emesh_dstaddr_inb;
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output [31:0] emesh_srcaddr_inb;
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output [31:0] emesh_data_inb;
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output emesh_wr_wait_inb;
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output emesh_rd_wait_inb;
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//# To the chip (hsmc port)
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output [7:0] txo_data_p;
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output [7:0] txo_data_n;
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output txo_frame_p;
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output txo_frame_n;
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output txo_lclk_p;
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output txo_lclk_n;
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output rxi_wr_wait_p;
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output rxi_wr_wait_n;
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output rxi_rd_wait_p;
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output rxi_rd_wait_n;
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output rxi_cclk_p;
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output rxi_cclk_n;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [71:0] tx_in; // From ctrl_tx of ewrapper_link_transmitter.v
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// End of automatics
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//############
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//# REGS
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//############
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//############
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//# WIRES
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//############
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// wire [71:0] tx_in;
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// wire [63:0] txo_data_paral;
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// wire [7:0] txo_frame_paral;
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wire [63:0] rxi_data_paral;
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wire [7:0] rxi_frame_paral;
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wire [8:0] rx_in_p;
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wire [8:0] rx_in_n;
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wire [71:0] rx_out;
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wire rx_outclock;
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wire [8:0] tx_out_p;
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wire [8:0] tx_out_n;
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wire rxi_cclk;
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wire clk_fast_deg0;
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wire clk_slow_deg0;
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wire clk_fast_deg90;
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// wire clk_slow_deg45;
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wire rxi_wr_wait;
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wire rxi_rd_wait;
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wire txo_wr_wait;
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wire txo_rd_wait;
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// wire [7:0] cs_ila2_TRIG3;
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// wire [7:0] cs_ila3_TRIG3;
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// wire [35:0] CONTROL0;
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// wire [35:0] CONTROL1;
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// wire [35:0] CONTROL2;
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// wire [35:0] CONTROL3;
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//#######################
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//# LVDS RECEIVER
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//#######################
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assign rxi_data_paral[63:0] = rx_out[63:0];
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assign rxi_frame_paral[7:0] = rx_out[71:64];
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assign rx_in_p[8:0] = {rxi_frame_p,rxi_data_p[7:0]};
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assign rx_in_n[8:0] = {rxi_frame_n,rxi_data_n[7:0]};
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ewrapper_link_receiver ctrl_rx(.rxi_data (rxi_data_paral[63:0]),
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.rxi_frame (rxi_frame_paral[7:0]),
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.rxi_lclk (rx_outclock),
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/*AUTOINST*/
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// Outputs
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.rxi_wr_wait (rxi_wr_wait),
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.rxi_rd_wait (rxi_rd_wait),
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.emesh_clk_inb (emesh_clk_inb),
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.emesh_access_inb (emesh_access_inb),
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.emesh_write_inb (emesh_write_inb),
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.emesh_datamode_inb (emesh_datamode_inb[1:0]),
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.emesh_ctrlmode_inb (emesh_ctrlmode_inb[3:0]),
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.emesh_dstaddr_inb (emesh_dstaddr_inb[31:0]),
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.emesh_srcaddr_inb (emesh_srcaddr_inb[31:0]),
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.emesh_data_inb (emesh_data_inb[31:0]),
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// Inputs
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.reset (reset),
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.emesh_wr_wait_outb (emesh_wr_wait_outb),
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.emesh_rd_wait_outb (emesh_rd_wait_outb));
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ewrapper_io_rx_slow io_rx(// Outputs
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.CLK_DIV_OUT (rx_outclock),
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.DATA_IN_TO_DEVICE (rx_out[71:0]),
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// Inputs
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.CLK_IN_P (rxi_lclk_p),
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.CLK_IN_N (rxi_lclk_n),
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.CLK_RESET (reset),
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.IO_RESET (reset),
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.DATA_IN_FROM_PINS_P(rx_in_p[8:0]),
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.DATA_IN_FROM_PINS_N(rx_in_n[8:0]),
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.BITSLIP (1'b0));
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// xilinx ISERDESE2 ip instantiation
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// !!! Make sure that the DIFF_TERM attribute of IBUFDS and IBUFGDS
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// !!! is set to TRUE inside ewrapper_io_rx.v
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//ewrapper_io_rx io_rx(// Inputs
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// .CLK_IN_P (rxi_lclk_p),
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// .CLK_IN_N (rxi_lclk_n),
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// .DATA_IN_FROM_PINS_P (rx_in_p[8:0]),
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// .DATA_IN_FROM_PINS_N (rx_in_n[8:0]),
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// .BITSLIP (1'b0),
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// .CLK_RESET (reset),
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// .IO_RESET (reset),
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// // Outputs
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// .DATA_IN_TO_DEVICE (rx_out[71:0]),
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// .CLK_DIV_OUT (rx_outclock));
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//#######################
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//# LVDS TRANSMITTER
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//#######################
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// assign tx_in[71:0] = {txo_frame_paral[7:0],txo_data_paral[63:0]};
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assign txo_frame_p = tx_out_p[8];
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assign txo_frame_n = tx_out_n[8];
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assign txo_data_p[7:0] = tx_out_p[7:0];
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assign txo_data_n[7:0] = tx_out_n[7:0];
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ewrapper_link_transmitter ctrl_tx(.txo_lclk (clk_slow_deg0),
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/*AUTOINST*/
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// Outputs
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.emesh_wr_wait_inb (emesh_wr_wait_inb),
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.emesh_rd_wait_inb (emesh_rd_wait_inb),
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.tx_in (tx_in[71:0]),
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// Inputs
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.reset (reset),
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.emesh_clk_inb (emesh_clk_inb),
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.emesh_access_outb (emesh_access_outb),
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.emesh_write_outb (emesh_write_outb),
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.emesh_datamode_outb(emesh_datamode_outb[1:0]),
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.emesh_ctrlmode_outb(emesh_ctrlmode_outb[3:0]),
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.emesh_dstaddr_outb(emesh_dstaddr_outb[31:0]),
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.emesh_srcaddr_outb(emesh_srcaddr_outb[31:0]),
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.emesh_data_outb (emesh_data_outb[31:0]),
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.txo_wr_wait (txo_wr_wait),
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.txo_rd_wait (txo_rd_wait),
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.burst_en (burst_en));
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// xilinx MMCME2_ADV ip instantiation
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io_clock_gen io_clock_gen(// Inputs
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.CLK_IN1 (clkin_100),
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.RESET (reset),
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// Outputs
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.CLK_OUT1 (rxi_cclk),
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.CLK_OUT2 (clk_fast_deg0),
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.CLK_OUT3 (clk_slow_deg0),
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.CLK_OUT4 (clk_fast_deg90),
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.LOCKED ());
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ewrapper_io_tx_slow io_tx(// Outputs
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.DATA_OUT_TO_PINS_P(tx_out_p[8:0]),
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.DATA_OUT_TO_PINS_N(tx_out_n[8:0]),
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.LCLK_OUT_TO_PINS_P(txo_lclk_p),
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.LCLK_OUT_TO_PINS_N(txo_lclk_n),
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// Inputs
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.CLK_IN (clk_fast_deg0),
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.CLK_IN_90 (clk_fast_deg90),
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.CLK_DIV_IN (clk_slow_deg0),
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.CLK_RESET (reset),
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.IO_RESET (reset),
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.DATA_OUT_FROM_DEVICE(tx_in[71:0]));
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// xilinx ISERDESE2 ip instantiation
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//
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// ewrapper_io_tx io_tx(// Inputs
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// .CLK_IN (clk_fast_deg0),
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// .CLK_DIV_IN (clk_slow_deg0),
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// .DATA_OUT_FROM_DEVICE (tx_in[71:0]),
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// .CLK_RESET (reset),
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// .IO_RESET (reset),
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// // Outputs
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// .DATA_OUT_TO_PINS_P (tx_out_p[8:0]),
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// .DATA_OUT_TO_PINS_N (tx_out_n[8:0]));
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// io_clock_fwd io_clock_fwd(// Inputs
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// .CLK_IN (clk_fast_deg45),
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// .CLK_DIV_IN (clk_slow_deg45),
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// .DATA_OUT_FROM_DEVICE (8'b01010101),
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// .CLK_RESET (reset),
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// .IO_RESET (reset),
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// // Outputs
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// .DATA_OUT_TO_PINS_P (txo_lclk_p),
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// .DATA_OUT_TO_PINS_N (txo_lclk_n));
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// xilinx OBUFDS instantiation
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//
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OBUFDS #(.IOSTANDARD ("LVDS_25")) obufds_cclk_inst (.O (rxi_cclk_p),
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.OB (rxi_cclk_n),
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.I (rxi_cclk));
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OBUFDS #(.IOSTANDARD ("LVDS_25")) rxi_wr_wait_inst (.O (rxi_wr_wait_p),
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.OB (rxi_wr_wait_n),
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.I (rxi_wr_wait));
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OBUFDS #(.IOSTANDARD ("LVDS_25")) rxi_rd_wait_inst (.O (rxi_rd_wait_p),
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.OB (rxi_rd_wait_n),
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.I (rxi_rd_wait));
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// xilinx IBUFDS instantiation
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//
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IBUFDS #(.DIFF_TERM ("TRUE"), // Differential termination
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.IOSTANDARD ("LVDS_25")) txo_wr_wait_inst (.I (txo_wr_wait_p),
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.IB (txo_wr_wait_n),
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.O (txo_wr_wait));
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// IBUFDS #(.DIFF_TERM ("TRUE"), // Differential termination
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// .IOSTANDARD ("LVDS_25")) txo_rd_wait_inst (.I (txo_rd_wait_p),
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// .IB (txo_rd_wait_n),
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// .O (txo_rd_wait));
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//No need for differential buffer
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//TODO:Need to clean up this hierarchy, make IP less technology dependant.
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assign txo_rd_wait = txo_rd_wait_p;
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//#################################
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//# Chip Scope Instantiation
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//#################################
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// assign cs_ila2_TRIG3[7:0] = {emesh_wr_wait_inb,
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// emesh_rd_wait_inb,
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// emesh_ctrlmode_outb[1:0],
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// emesh_datamode_outb[1:0],
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// emesh_write_outb,
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// emesh_access_outb};
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// assign cs_ila3_TRIG3[7:0] = {emesh_wr_wait_outb,
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// emesh_rd_wait_outb,
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// emesh_ctrlmode_inb[1:0],
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// emesh_datamode_inb[1:0],
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// emesh_write_inb,
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// emesh_access_inb};
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// cs_ila0 cs_ila0(.TRIG0 (tx_in[71:0]),
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// .CONTROL (CONTROL0[35:0]),
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// .CLK (clk_slow_deg0));
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// cs_ila0 cs_ila1(.TRIG0 (rx_out[71:0]),
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// .CONTROL (CONTROL1[35:0]),
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// .CLK (emesh_clk_inb));
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// cs_ila1 cs_ila2(.TRIG0 (emesh_dstaddr_outb[31:0]),
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// .TRIG1 (emesh_data_outb[31:0]),
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// .TRIG2 (emesh_srcaddr_outb[31:0]),
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// .TRIG3 (cs_ila2_TRIG3[7:0]),
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// .CONTROL (CONTROL2[35:0]),
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// .CLK (emesh_clk_inb));
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// cs_ila1 cs_ila3(.TRIG0 (emesh_dstaddr_inb[31:0]),
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// .TRIG1 (emesh_data_inb[31:0]),
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// .TRIG2 (emesh_srcaddr_inb[31:0]),
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// .TRIG3 (cs_ila3_TRIG3[7:0]),
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// .CONTROL (CONTROL3[35:0]),
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// .CLK (emesh_clk_inb));
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// cs_icon cs_icon(.CONTROL0 (CONTROL0[35:0]),
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// .CONTROL1 (CONTROL1[35:0]),
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// .CONTROL2 (CONTROL2[35:0]),
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// .CONTROL3 (CONTROL3[35:0]));
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endmodule // ewrapper_link_top
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