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57 lines
1.6 KiB
Verilog
57 lines
1.6 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module debouncer (/*AUTOARG*/
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// Outputs
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clean_out,
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// Inputs
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clk, noisy_in
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);
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parameter N = 20; //debouncer counter width
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input clk; //system clock
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input noisy_in; //bouncy input (convention says it goes low when button is pressed)
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output clean_out; //clean output (positive polarity)
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wire expired;
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wire sync_in;
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reg [N-1:0] counter;
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wire filtering;
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synchronizer #(1) synchronizer(.out (sync_in),
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.in (noisy_in),
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.clk (clk),
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.reset (1'b0));
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//Counter that resets when sync_in is low
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always @ (posedge clk)
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if(sync_in)
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counter[N-1:0]={(N){1'b1}};
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else if(filtering)
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counter[N-1:0]=counter[N-1:0]-1'b1;
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assign filtering =|counter[N-1:0];
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assign clean_out = filtering | sync_in;
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endmodule // debouncer
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