mirror of
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199 lines
6.8 KiB
Verilog
199 lines
6.8 KiB
Verilog
/*
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File: ewrapper_link_receiver.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module ewrapper_link_receiver (/*AUTOARG*/
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// Outputs
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rxi_wr_wait, rxi_rd_wait, emesh_clk_inb, emesh_access_inb,
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emesh_write_inb, emesh_datamode_inb, emesh_ctrlmode_inb,
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emesh_dstaddr_inb, emesh_srcaddr_inb, emesh_data_inb,
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// Inputs
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reset, rxi_data, rxi_lclk, rxi_frame, emesh_wr_wait_outb,
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emesh_rd_wait_outb
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);
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//#########
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//# INPUTS
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//#########
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input reset; //reset input
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//# From the lvds-serdes
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input [63:0] rxi_data; //Eight Parallel Byte words
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input rxi_lclk; //receive clock (synchronized to the data)
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input [7:0] rxi_frame; //Parallel frame signals representing
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// 4 transmission clock cycles
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//# From the emesh interface
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input emesh_wr_wait_outb;
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input emesh_rd_wait_outb;
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//##########
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//# OUTPUTS
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//##########
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//# To the transmitter
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output rxi_wr_wait; //wait indicator
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output rxi_rd_wait; //wait indicator
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//# To the emesh interface
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output emesh_clk_inb;
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output emesh_access_inb;
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output emesh_write_inb;
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output [1:0] emesh_datamode_inb;
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output [3:0] emesh_ctrlmode_inb;
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output [31:0] emesh_dstaddr_inb;
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output [31:0] emesh_srcaddr_inb;
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output [31:0] emesh_data_inb;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//#########
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//# Wires
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//#########
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wire emesh_wr_access_inb;
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wire emesh_wr_write_inb;
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wire [1:0] emesh_wr_datamode_inb;
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wire [3:0] emesh_wr_ctrlmode_inb;
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wire [31:0] emesh_wr_dstaddr_inb;
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wire [31:0] emesh_wr_srcaddr_inb;
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wire [31:0] emesh_wr_data_inb;
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wire emesh_rd_access_inb;
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wire emesh_rd_write_inb;
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wire [1:0] emesh_rd_datamode_inb;
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wire [3:0] emesh_rd_ctrlmode_inb;
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wire [31:0] emesh_rd_dstaddr_inb;
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wire [31:0] emesh_rd_srcaddr_inb;
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wire [31:0] emesh_rd_data_inb;
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wire select_write_tran;
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wire wr_wait;
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wire rd_wait;
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wire emesh_access_tmp;
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//###############
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//# Emesh clock
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//###############
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assign emesh_clk_inb = rxi_lclk;
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//######################################
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//# Write-Read Transactions Arbitration
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//# Write has a higher priority ALWAYS
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//######################################
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assign select_write_tran = emesh_wr_access_inb & ~emesh_wr_wait_outb;
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assign emesh_access_inb = emesh_access_tmp & ~emesh_wr_wait_outb;
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assign wr_wait = emesh_wr_wait_outb;
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assign rd_wait = emesh_rd_access_inb & select_write_tran |
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(emesh_wr_wait_outb | emesh_rd_wait_outb);
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assign emesh_srcaddr_inb[31:0] =
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select_write_tran ? emesh_wr_srcaddr_inb[31:0] :
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emesh_rd_srcaddr_inb[31:0];
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assign emesh_dstaddr_inb[31:0] =
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select_write_tran ? emesh_wr_dstaddr_inb[31:0] :
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emesh_rd_dstaddr_inb[31:0];
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assign emesh_datamode_inb[1:0] =
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select_write_tran ? emesh_wr_datamode_inb[1:0] :
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emesh_rd_datamode_inb[1:0];
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assign emesh_ctrlmode_inb[3:0] =
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select_write_tran ? emesh_wr_ctrlmode_inb[3:0] :
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emesh_rd_ctrlmode_inb[3:0];
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assign emesh_data_inb[31:0] = select_write_tran ? emesh_wr_data_inb[31:0] :
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emesh_rd_data_inb[31:0];
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assign emesh_access_tmp = select_write_tran ? emesh_wr_access_inb :
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emesh_rd_access_inb;
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assign emesh_write_inb = select_write_tran ? emesh_wr_write_inb :
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emesh_rd_write_inb;
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//############################################
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//# Write Transactions Receiver Instantiation
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//############################################
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/*ewrapper_link_rxi AUTO_TEMPLATE(
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.rxi_rd (1'b0),
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.emesh_wait_outb (wr_wait),
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.rxi_wait (rxi_wr_wait),
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.emesh_\(.*\) (emesh_wr_\1[]),
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);
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*/
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ewrapper_link_rxi wr_rxi(/*AUTOINST*/
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// Outputs
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.rxi_wait (rxi_wr_wait), // Templated
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.emesh_access_inb (emesh_wr_access_inb), // Templated
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.emesh_write_inb (emesh_wr_write_inb), // Templated
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.emesh_datamode_inb (emesh_wr_datamode_inb[1:0]), // Templated
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.emesh_ctrlmode_inb (emesh_wr_ctrlmode_inb[3:0]), // Templated
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.emesh_dstaddr_inb (emesh_wr_dstaddr_inb[31:0]), // Templated
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.emesh_srcaddr_inb (emesh_wr_srcaddr_inb[31:0]), // Templated
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.emesh_data_inb (emesh_wr_data_inb[31:0]), // Templated
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// Inputs
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.reset (reset),
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.rxi_data (rxi_data[63:0]),
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.rxi_lclk (rxi_lclk),
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.rxi_frame (rxi_frame[7:0]),
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.emesh_wait_outb (wr_wait), // Templated
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.rxi_rd (1'b0)); // Templated
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//############################################
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//# Read Transactions Receiver Instantiation
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//############################################
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/*ewrapper_link_rxi AUTO_TEMPLATE(
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.rxi_rd (1'b1),
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.emesh_wait_outb (rd_wait),
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.rxi_wait (rxi_rd_wait),
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.emesh_\(.*\) (emesh_rd_\1[]),
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);
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*/
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ewrapper_link_rxi rd_rxi(/*AUTOINST*/
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// Outputs
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.rxi_wait (rxi_rd_wait), // Templated
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.emesh_access_inb (emesh_rd_access_inb), // Templated
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.emesh_write_inb (emesh_rd_write_inb), // Templated
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.emesh_datamode_inb (emesh_rd_datamode_inb[1:0]), // Templated
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.emesh_ctrlmode_inb (emesh_rd_ctrlmode_inb[3:0]), // Templated
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.emesh_dstaddr_inb (emesh_rd_dstaddr_inb[31:0]), // Templated
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.emesh_srcaddr_inb (emesh_rd_srcaddr_inb[31:0]), // Templated
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.emesh_data_inb (emesh_rd_data_inb[31:0]), // Templated
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// Inputs
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.reset (reset),
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.rxi_data (rxi_data[63:0]),
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.rxi_lclk (rxi_lclk),
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.rxi_frame (rxi_frame[7:0]),
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.emesh_wait_outb (rd_wait), // Templated
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.rxi_rd (1'b1)); // Templated
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endmodule // ewrapper_link_receiver
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