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59 lines
1.6 KiB
Verilog
59 lines
1.6 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module synchronizer #(parameter DW=32) (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in, clk, reset
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);
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//Input Side
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input [DW-1:0] in;
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input clk;
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input reset;//asynchronous signal
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//Output Side
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output [DW-1:0] out;
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reg [DW-1:0] sync_reg0;
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reg [DW-1:0] sync_reg1;
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reg [DW-1:0] out;
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//Synchronization between clock domain
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//We use two flip-flops for metastability improvement
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always @ (posedge clk or posedge reset)
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if(reset)
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begin
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sync_reg0[DW-1:0] <= {(DW){1'b0}};
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sync_reg1[DW-1:0] <= {(DW){1'b0}};
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out[DW-1:0] <= {(DW){1'b0}};
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end
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else
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begin
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sync_reg0[DW-1:0] <= in[DW-1:0];
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sync_reg1[DW-1:0] <= sync_reg0[DW-1:0];
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out[DW-1:0] <= sync_reg1[DW-1:0];
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end
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endmodule // clock_synchronizer
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