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233 lines
7.6 KiB
Verilog
233 lines
7.6 KiB
Verilog
/*
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File: ewrapper_link_transmitter.v
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This file is part of the Parallella FPGA Reference Design.
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Roman Trogan <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module ewrapper_link_transmitter(/*AUTOARG*/
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// Outputs
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emesh_wr_wait_inb, emesh_rd_wait_inb, tx_in,
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// Inputs
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reset, txo_lclk, emesh_clk_inb, emesh_access_outb,
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emesh_write_outb, emesh_datamode_outb, emesh_ctrlmode_outb,
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emesh_dstaddr_outb, emesh_srcaddr_outb, emesh_data_outb,
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txo_wr_wait, txo_rd_wait, burst_en
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);
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//#########
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//# INPUTS
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//#########
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input reset; //reset input
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input txo_lclk; //transmitter clock
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input emesh_clk_inb; // clock of the incoming emesh transaction
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//# From the Emesh
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input emesh_access_outb;
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input emesh_write_outb;
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input [1:0] emesh_datamode_outb;
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input [3:0] emesh_ctrlmode_outb;
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input [31:0] emesh_dstaddr_outb;
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input [31:0] emesh_srcaddr_outb;
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input [31:0] emesh_data_outb;
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//# From the receiver
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input txo_wr_wait; //wait indicator
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input txo_rd_wait; //wait indicator
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input burst_en; // Burst enable control
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//##########
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//# OUTPUTS
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//##########
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//# To the Emesh
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output emesh_wr_wait_inb;
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output emesh_rd_wait_inb;
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//# To the lvds-serdes
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output [71:0] tx_in;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//#########
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//# Regs
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//#########
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reg wrfifo_rd_en;
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//#########
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//# Wires
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//#########
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wire [1:0] txo_wait;
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wire [1:0] txo_wait_sync;
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wire txo_wr_wait_sync;
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wire txo_rd_wait_sync;
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wire [103:0] fifo_in;
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wire [103:0] fifo_out;
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wire [107:0] wrfifo_out;
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wire [107:0] rdfifo_out;
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wire wrfifo_wait;
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wire rdfifo_wait;
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wire wrfifo_rd_int;
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wire rdfifo_rd_int;
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wire wrfifo_rd;
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wire rdfifo_rd;
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wire wrfifo_wr;
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wire rdfifo_wr;
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wire rdfifo_empty;
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wire wrfifo_empty;
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wire txo_emesh_wait;
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wire txo_emesh_access;
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wire txo_emesh_write;
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wire [1:0] txo_emesh_datamode;
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wire [3:0] txo_emesh_ctrlmode;
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wire [31:0] txo_emesh_dstaddr;
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wire [31:0] txo_emesh_srcaddr;
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wire [31:0] txo_emesh_data;
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//############################
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//# txo_wait synchronization
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//############################
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assign txo_wait[1:0] = {txo_rd_wait,txo_wr_wait};
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assign txo_wr_wait_sync = txo_wait_sync[0];
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assign txo_rd_wait_sync = txo_wait_sync[1];
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synchronizer #(.DW(2)) synchronizer(.out (txo_wait_sync[1:0]),
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.in (txo_wait[1:0]),
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.clk (txo_lclk),
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.reset (reset));
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//#####################################
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//# lvds_link_txo instantiation
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//#####################################
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ewrapper_link_txo txo(/*AUTOINST*/
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// Outputs
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.txo_emesh_wait (txo_emesh_wait),
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.tx_in (tx_in[71:0]),
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// Inputs
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.reset (reset),
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.txo_lclk (txo_lclk),
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.txo_emesh_access (txo_emesh_access),
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.txo_emesh_write (txo_emesh_write),
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.txo_emesh_datamode (txo_emesh_datamode[1:0]),
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.txo_emesh_ctrlmode (txo_emesh_ctrlmode[3:0]),
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.txo_emesh_dstaddr (txo_emesh_dstaddr[31:0]),
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.txo_emesh_srcaddr (txo_emesh_srcaddr[31:0]),
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.txo_emesh_data (txo_emesh_data[31:0]),
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.burst_en (burst_en));
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//#####################################
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//# synchronization FIFOs (read/write)
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//#####################################
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//# FIFO writes
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assign wrfifo_wr = emesh_access_outb & emesh_write_outb & ~emesh_wr_wait_inb;
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assign rdfifo_wr = emesh_access_outb &~emesh_write_outb & ~emesh_rd_wait_inb;
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//# FIFO reads
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assign wrfifo_rd_int = ~(wrfifo_empty | txo_wr_wait_sync | txo_emesh_wait);
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assign rdfifo_rd_int = ~(rdfifo_empty | txo_rd_wait_sync | txo_emesh_wait);
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//# arbitration
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always @ (posedge txo_lclk or posedge reset)
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if(reset)
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wrfifo_rd_en <= 1'b0;
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else
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wrfifo_rd_en <= ~wrfifo_rd_en;
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assign wrfifo_rd = wrfifo_rd_int & ( wrfifo_rd_en | ~rdfifo_rd_int);
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assign rdfifo_rd = rdfifo_rd_int & (~wrfifo_rd_en | ~wrfifo_rd_int);
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//# FIFO input
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assign fifo_in[103:0] = {emesh_srcaddr_outb[31:0],
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emesh_data_outb[31:0],
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emesh_dstaddr_outb[31:0],
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emesh_ctrlmode_outb[3:0],
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emesh_datamode_outb[1:0],
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emesh_write_outb,
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emesh_access_outb};
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//# FIFO output
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assign fifo_out[103:0] = wrfifo_rd ? wrfifo_out[103:0] : rdfifo_out[103:0];
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assign txo_emesh_access = wrfifo_rd | rdfifo_rd;
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assign txo_emesh_write = fifo_out[1];
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assign txo_emesh_datamode[1:0] = fifo_out[3:2];
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assign txo_emesh_ctrlmode[3:0] = fifo_out[7:4];
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assign txo_emesh_dstaddr[31:0] = fifo_out[39:8];
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assign txo_emesh_data[31:0] = fifo_out[71:40];
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assign txo_emesh_srcaddr[31:0] = fifo_out[103:72];
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/*fifo AUTO_TEMPLATE(.rd_clk (txo_lclk),
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.wr_clk (emesh_clk_inb),
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.wr_data (fifo_in[103:0]),
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.rd_data (wrfifo_out[103:0]),
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.rd_fifo_empty (wrfifo_empty),
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.wr_fifo_full (emesh_wr_wait_inb),
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.wr_write (wrfifo_wr),
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.rd_read (wrfifo_rd),
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);
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*/
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//# We have 4 entries of 104 bits each
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fifo #(.DW(104), .AW(2)) wrfifo_txo(/*AUTOINST*/
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// Outputs
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.rd_data (wrfifo_out[103:0]), // Templated
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.rd_fifo_empty (wrfifo_empty), // Templated
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.wr_fifo_full (emesh_wr_wait_inb), // Templated
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// Inputs
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.reset (reset),
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.wr_clk (emesh_clk_inb), // Templated
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.rd_clk (txo_lclk), // Templated
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.wr_write (wrfifo_wr), // Templated
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.wr_data (fifo_in[103:0]), // Templated
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.rd_read (wrfifo_rd)); // Templated
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/*fifo AUTO_TEMPLATE(.rd_clk (txo_lclk),
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.wr_clk (emesh_clk_inb),
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.wr_data (fifo_in[103:0]),
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.rd_data (rdfifo_out[103:0]),
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.rd_fifo_empty (rdfifo_empty),
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.wr_fifo_full (emesh_rd_wait_inb),
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.wr_write (rdfifo_wr),
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.rd_read (rdfifo_rd),
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);
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*/
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//# We have 4 entries of 104 bits each
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fifo #(.DW(104), .AW(2)) rdfifo_txo(/*AUTOINST*/
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// Outputs
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.rd_data (rdfifo_out[103:0]), // Templated
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.rd_fifo_empty (rdfifo_empty), // Templated
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.wr_fifo_full (emesh_rd_wait_inb), // Templated
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// Inputs
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.reset (reset),
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.wr_clk (emesh_clk_inb), // Templated
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.rd_clk (txo_lclk), // Templated
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.wr_write (rdfifo_wr), // Templated
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.wr_data (fifo_in[103:0]), // Templated
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.rd_read (rdfifo_rd)); // Templated
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endmodule // ewrapper_link_transmitter
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